DETAILED ACTION
Claims 1-20 are pending.
Claims 10-20 have been withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 1 (and similarly claim 9) is objected to because of the following informalities:
In lines 5-6, replace “each instruction” with --each instruction of the plurality of instructions-- to make it more clear that not every instruction of the program includes the claimed indication. Applicant could reword the entire paragraph to
--receiving, from a computer program, a plurality of instructions, each instruction of the plurality of instructions representing a respective indirect branch of the computer program and having a respective indicator indicating one of context-sensitive (CS) and context-insensitive (CIS);-- (or the like).
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
Such claim limitations are:
In claim 2, “determining, at the first processing unit…whether the respective directory…has therein the corresponding existing entry”. From paragraph 48, the first processing unit corresponds to FIG.7, 701. The structure that performs the actual determining, while not explicitly disclosed, corresponds to implied comparison circuitry that compares the output of 704 to a tag 703 to determine if there is a match/hit (paragraph 49). Thus, the claimed first processing unit encompasses at least a hardware comparator (and equivalents thereof).
In claim 2, “determining, at the second processing unit… whether the respective directory…has therein the corresponding existing entry”. From paragraph 48, the second processing unit corresponds to FIG.7, 702. The structure that performs the actual determining, while not explicitly disclosed, corresponds to implied comparison circuitry that compares the output of 704 to a tag 703 to determine if there is a match/hit (paragraph 50). Thus, the claimed second processing unit encompasses at least a hardware comparator (and equivalents thereof).
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 6 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Applicant now claims that random or LRU replacement is initiated for each CIS and CS branch lacking an entry in the respective directory. The examiner cannot find original support for this limitation for each CIS/CS branch. While paragraph 53 of the specification states that random/LRU replacement schemes can be used, neither is disclosed as being used for each branch lacking an entry. As the most extreme example, when the system powers on and starts executing a program, it is the examiner’s understanding that there would be no entries in the directories. Thus, for the first CS/CIS branch, there is nothing to replace via random/LRU replacement. Replacement is generally known in the art to occur when there is no room to put a new entry (e.g. when a directory is full and there are no vacant entries). As such, applicant’s claim 6 is directed to an embodiment not originally described, i.e. new matter. Instead of referring to “each”, applicant could claim that one of the replacement schemes is initiated for a “given” branch indicating CIS/CS. For purposes of prior art rejection under Chen, the claim will be interpreted as if “given” were used instead of “each”. For purposes of prior art rejection under Farooq, the claim will be interpreted as written (due to time constraints in maintaining a second grounds of rejection).
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims recite the following limitations for which there is a lack of antecedent basis:
In claim 2, line 1, “the electronic device”. Please replace with --the processor--.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 6,721,877) in view of the English translation of JP2002189529 (herein referred to as Seiji).
Referring to claim 1, Chen has taught a method comprising, at a processor (FIG.8, processor 10) including a first processing unit (FIG.6, at least 94) and a second processing unit (FIG.6, at least 92) each coupled to tangible, non-transitory processor-readable memory (FIG.8 shows the processor 10 connected to DRAM (non-transitory memory) 204 (column 23, lines 5-10). FIG.1 shows processor 10 in more detail, including branch prediction unit 18, which is shown in detail in FIG.6. Thus, the processing units (at least 92 and 94) of the branch prediction unit of the processor are coupled to the memory):
receiving, from a computer program, a plurality of instructions each representing a respective indirect branch of the computer program (from column 23, lines 5-10, the processor 10 receives instructions from a computer program, including indirect branch instructions (e.g. see the abstract) for which predictions are tracked by predictors in FIG.6), each instruction having a respective indicator indicating one of context-sensitive (CS) and context-insensitive (CIS) (see FIG.6, and note the S-bit in 94. From column 19, lines 50-66, this bit is associated with an indirect branch instruction and indicates whether the branch instruction is context-sensitive (i.e., predicted by directory 92, which receives an index from 90 based on the branch PC (from 18D) and historical context 98) or context-insensitive (i.e., predicted by directory 94, which only receives an index based on the branch PC and not additional context 98));
providing, for each instruction of the plurality of instructions having a corresponding existing entry in at least one of a respective directory at each of the first processing unit and the second processing unit, a respective target identifier of the corresponding existing entry, the target identifier for each instruction identifying a respective target for the respective indirect branch (from FIG.6, note that when either or both of directories 92 and 94 have an entry that corresponds to the indirect branch instruction, a predicted target address is provided to selector 96);
generating, for each instruction of the plurality of instructions associated with CIS and lacking the corresponding existing entry in the respective directory at each of the first processing unit and the second processing unit, a corresponding instant entry in the respective directory at the first processing unit (context-insensitive branches will be allocated entries in first processing unit 94. Predictors, as known, are initially empty, and populated as branches are encountered. When a branch is encountered and there is no prediction entry, a prediction entry will be created for that branch to predict future instances of that branch); and
generating, for each instruction of the plurality of instructions associated with CS and lacking the corresponding existing entry in the respective directory at each of the first processing unit and the second processing unit, a corresponding instant entry in the respective directory at the second processing unit (context-sensitive branches will be allocated entries in second processing unit 92. Again, as known, predictors, as known, are initially empty, and populated as branches are encountered);
wherein the respective target identifier is provided for, among the plurality of instructions, at least one instruction associated with CS and at least one instruction associated with CIS (again, units 94 and 92 will provide target identifiers for CIS and CS indirect branches, respectively);
wherein the corresponding instant entry is generated in the respective directory at the first processing unit for, among the plurality of instructions, a further at least one instruction associated with CIS (again, any CIS indirect branch will have an entry generated in directory 94); and
wherein the corresponding instant entry is generated in the respective directory at the second processing unit for, among the plurality of instructions, a further at least one instruction associated with CS (again, any CS indirect branch will have an entry generated in directory 92).
Chen has not taught that the instructions themselves indicate CS and CIS. Instead, the S-bit in directory 94 does the CS/CIS indicating. However, Seiji has taught that a compiler may analyze an indirect branch and set an indicator in an empty field of the branch instruction to indicate to the hardware whether or not the branch has a fixed target address (CIS) (see paragraph 55). One of ordinary skill in the art would have recognized that such could be substituted for the S-bit of Chen to achieve predictable results. Having a compiler identify CIS/CS would simplify the hardware design by reducing the amount of storage required to implement directory 94 (the S-bit no longer needs to be stored), and by eliminating the need for the hardware to learn and track, at runtime, which branches are CS and which are CIS. Further and optionally, the predictor’s power consumption could be reduced because the access to both 92 and 94 for a given branch could be eliminated. Instead, because the instruction would indicate which directory will be used, just that directory may be accessed, thereby reducing power by not accessing the other directory. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute Seiji’s indications for Chen’s tracked S-bit. The resulting prediction system would work substantially the same way. When an indirect branch is determined by a compiler to be CS, the CS indicator would cause either an entry to be allocated in 92 (if one does not exist) or a predicted target address to be provided from 92. And, when an indirect branch is determined by a compiler to be CIS, the CIS bit would cause either an entry to be allocated in 94 (if one does not exist) or a predicted target address to be provided from 94.
Referring to claim 7, Chen, as modified, has taught the method of claim 1 wherein the indicator of each instruction is a label of one of CS and CIS (at least one bit is needed to encode fixed (CIS) or not-fixed (CIS) in Chen as modified by Seiji. For instance, bit=0 is a label that indicates the indirect branch is context-insensitive, while bit=1 is a label that indicates that the indirect branch is context-sensitive (or vice-versa)).
Claim 9 is mostly rejected for similar reasoning as claim 1. Note that the non-transitory processor-readable memory has stored thereon instructions to cause a processor to perform the claimed steps (e.g. see FIG.1, instruction cache 14, or FIG.8, main memory 204 (column 23, lines 5-10)).
Claims 2-6 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Siji and the examiner’s taking of Official Notice.
Referring to claim 2, Chen, as modified, has taught the method of claim 1 further comprising, at the electronic device:
determining, at the first processing unit for each instruction of the plurality of instructions indicating CIS, whether the respective directory at the first processing unit has therein the corresponding existing entry (again, when a branch indicates CIS, it will be determined whether directory 94 includes an entry to predict that branch); and
determining, at the second processing unit for each instruction of the plurality of instructions indicating CS, whether the respective directory at the second processing unit has therein the corresponding existing entry (when a branch indicates CS, it will be determined whether directory 92 includes an entry to predict that branch).
Chen has not taught that the first and second processing units include a comparator circuit to make the determination (as per 112(f) interpretation). However, from column 20, lines 36-44, and column 14, line 54, to column 15, line 22, Chen states that the directories may be tagless, which implies they could be tagged (and thus require a comparator to compare the tag). Chen also points out a benefit of using tags - to reduce the likelihood that two different branches map to the same entry, and thereby reduce chances of using a prediction not meant for a branch (which may increase chances of misprediction and expensive recovery). As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen such that the first and second processing units include a comparator circuit.
Referring to claim 3, Chen, as modified, has taught the method of claim 1 but has not taught wherein each corresponding existing entry of the respective directory at the first processing unit includes a respective tag including a respective hash of a respective program counter. From column 20, lines 36-44, and column 14, line 54, to column 15, line 22, Chen states that the directories may be tagless, but also points out a benefit of using tags - to reduce the likelihood that two different branches map to the same entry, and thereby using a prediction not meant for a branch (which may increase chances of misprediction and expensive recovery). Official Notice is taken that hashing a program counter and comparing the result to a tag was well-known in the art before applicant's invention. Again, this could help reduce aliasing (mapping of two or more branches to the same entry). Hashing may also reduce the number of bits used to locate the entry by reducing the program counter (or a portion thereof) to a smaller number of bits. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen such that each corresponding existing entry of the respective directory at the first processing unit includes a respective tag including a respective hash of a respective program counter.
Referring to claim 4, Chen, as modified, has taught the method of claim 1 including performing a respective hash of a respective program counter and respective context information (FIG.9, hash unit 90, which hashes the program counter (“Branch PC”) and context information from 98 using XOR (column 21, lines 31-58)). Chen has not taught herein each corresponding respective existing entry of the respective directory at the second processing unit includes a respective tag including the hash. However, for reasons set forth in the rejection of claim 3, it is obvious to include a tag to be compared to the hash output.
Referring to claim 5, Chen, as modified, has taught the method of claim 4 wherein the respective context information of each tag includes at least one of a respective branch address (from FIG.6, branch addresses from 98 are used in the hash), a respective branch taken and not-taken history, and respective function call stack contents.
Referring to claim 6, Chen, as modified, has taught the method of claim 1 but has not taught wherein generating, for each instruction of the plurality of instructions indicating CIS and lacking the corresponding existing entry in the respective directory at each of the first processing unit and the second processing unit, the corresponding instant entry in the respective directory at the first processing unit and generating, for each instruction of the plurality of instructions indicating CS and lacking the corresponding existing entry in the respective directory at each of the first processing unit and the second processing unit, the corresponding instant entry in the respective directory at the second processing unit includes: initiating one of a random replacement and a least recently used replacement to complete the corresponding instant entry in accordance with the respective target for the respective indirect branch of the computer program. However, Official Notice is taken that replacing an entry in a full predictor using either a random or LRU scheme was well-known in the art before applicant's invention. Temporal locality is the principle where a recently accessed memory location is likely to be accessed again in the near future. Therefore, a new branch is likely to be accessed again in the near future and, thus, creating a prediction entry for that branch would be beneficial. An issue arises if the predictor is full. In such a case, the system would benefit by replacing a previous branch to accommodate the new branch (to take advantage of temporal locality). LRU is known to remove the oldest unused prediction, thereby potentially replacing an unneeded prediction with one more likely to be used. Random replacement on the other hand is simply a fair scheme that doesn’t favor any particular branch. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen such that generating, for each instruction of the plurality of instructions indicating CIS and lacking the corresponding existing entry in the respective directory at each of the first processing unit and the second processing unit, the corresponding instant entry in the respective directory at the first processing unit and generating, for each instruction of the plurality of instructions indicating CS and lacking the corresponding existing entry in the respective directory at each of the first processing unit and the second processing unit, the corresponding instant entry in the respective directory at the second processing unit includes: initiating one of a random replacement and a least recently used replacement to complete the corresponding instant entry in accordance with the respective target for the respective indirect branch of the computer program.
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Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 9, 1-3, and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Farooq et al., “Compiler Support for Value-Based Indirect Branch Prediction”.
Referring to claim 9, Farooq has taught a non-transitory processor-readable memory (e.g. Table 2, instruction cache (I-cache)) having stored thereon instructions to cause a processor (Table 2 on p.193 refers to a processor with various parameters) including a first processing unit (FIG.2 on p.188, at least BTB) and a second processing unit (FIG.2, at least HIB) to:
receive, from a computer program, a plurality of instructions each representing a respective indirect branch of the computer program, each instruction having a respective indicator indicating one of context-sensitive (CS) and context-insensitive (CIS) (see bit 13 in FIG.4 on p.190. This is a 1-bit indicator that specifies VBBI or no VBBI. From section 2 and FIG.2, VBBI is used when a compiler detects that the target of an indirect branch instruction is correlated with some prior instruction. VBBI is used by storing the result of the prior instruction in the HIB so that the result can be used to determine a predicted target for the indirect branch instruction. As such, when bit 13 = 1, this indicates CS because the branch is sensitive to context provided by a prior instruction. When bit 13 = 0, VBBI is not used, which indicates CIS because the branch is insensitive to HIB data generated by a prior instruction);
provide, for each instruction of the plurality of instructions having a corresponding existing entry in at least one of a respective directory at each of the first processing unit and the second processing unit, a respective target identifier of the corresponding existing entry, the target identifier for each instruction identifying a respective target for the respective indirect branch (from FIG.2, when a CIS indirect branch entry exists in BTB, a predicted target address is provided. When a CS indirect branch entry exists in HIB, a value is provided which is combined with the PC to identify a predicted target address. As such, this value, which is propagated through the ‘1’ input of the MUX at the bottom of FIG.2, is a target identifier);
generate, for each instruction of the plurality of instructions indicating CIS and lacking the corresponding existing entry in the respective directory at each of the first processing unit and the second processing unit, a corresponding instant entry in the respective directory at the first processing unit (when bit 13 = 0, and there is no entry in the BTB for the branch, an entry will be created in the BTB. As is known, predictors are initially empty and are populated as branches are encountered); and
generate, for each instruction of the plurality of instructions indicating CS and lacking the corresponding existing entry in the respective directory at each of the first processing unit and the second processing unit, a corresponding instant entry in the respective directory at the second processing unit (for a branch with bit 13 = 1, there will be a preceding hint instruction. When there is no entry for the hint instruction in the HIB, an entry will be created for the hint instruction. As is known, predictors are initially empty and are populated as branches are encountered. This hint entry is generated for a CS branch);
wherein the plurality of instructions includes at least one instruction indicating CS and having the corresponding existing entry in the respective directory of at least one of the first processing unit and the second processing unit (again, for a branch with bit 13 = 1, there will be a hint entry in the second processing unit (HIB));
wherein the plurality of instructions includes at least one instruction indicating CIS and having the corresponding existing entry in the respective directory of at least one of the first processing unit and the second processing unit (again, for a branch with bit 13 = 0, there will be an entry in the first processing unit (BTB));
wherein the plurality of instructions includes at least one instruction indicating CS and lacking the corresponding existing entry in the respective directory at each of the first processing unit and the second processing unit (again, the BTB and HIB will initially have no entries (e.g. upon powering on/resetting the system). Thus, for any CS branch, an entry will need to be created in the HIB); and
wherein the plurality of instructions includes at least one instruction indicating CIS and lacking the corresponding existing entry in the respective directory at each of the first processing unit and the second processing unit (again, the BTB and HIB will initially have no entries (e.g. upon powering on/resetting the system). Thus, for any CIS branch, an entry will need to be created in the HIB).
Claim 1 is directed to the method performed by the processor of claim 9 and is, thus, rejected for similar reasoning as claim 9.
Referring to claim 2, Farooq has taught the method of claim 1 further comprising, at the electronic device:
determining, at the first processing unit for each instruction of the plurality of instructions indicating CIS, whether the respective directory at the first processing unit has therein the corresponding existing entry (again, when a branch indicates CIS, it will be determined whether BTB includes an entry to predict that branch. This is done by using the PC of the branch as an index into the BTB. Per Table 2, the BTB is set-associative, which means it has tags (as known in the art) and a comparator circuit to compare the tags); and
determining, at the second processing unit for each instruction of the plurality of instructions indicating CS, whether the respective directory at the second processing unit has therein the corresponding existing entry (for a branch indicating CS, it will be determined whether HIB includes an entry to predict that branch by comparing, with a circuit, the branch PC to the jmp_pc tag stored in HIB).
Referring to claim 3, Farooq, as modified, has taught the method of claim 1 wherein each corresponding existing entry of the respective directory at the first processing unit includes a respective tag including a respective hash of a respective program counter (from FIG.2, for a BTB access, a hash would be performed with the PC and 0 (since there is no hint). This would be compared to a tag, which exists for 4-way set associative BTBs (Table 2)).
Referring to claim 7, Farooq has taught the method of claim 1 wherein the respective indicator of each instruction is a label of one of CS and CIS (again, from FIG.4, a ‘1’ in bit 13 is a CS label and a ‘0’ in bit 13 is a CIS label).
Examiner Note
Because the examiner has already rejected the full set of claims under Chen, the examiner has not fully addressed the dependent claims with respect to Farooq at this time. However, this should not be interpreted as an indication that they are allowable over Farooq (unless otherwise indicated below). Should applicant amend to overcome Chen (in a manner other than simply writing a dependent claim into independent form), the examiner will reject the dependent claims with respect to Farooq at that time, where possible.
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
On page 17 of applicant’s response, applicant argues that Chen is silent towards generating entries.
Even if Chen is silent, this does not mean entries are not generated. The examiner asserts that one of ordinary skill in the art understands that entries are generated in tables 92 and 94 as branches are encountered (e.g. the first time they are encountered). This is how branch prediction works, where initially-empty tables are populated over time with prediction entries as branches are encountered.
On page 18 of applicant’s response, applicant argues that Farooq is silent towards generating entries at HIB or BTB for branches, a hint instruction writes to HIB at write-back, and writing entries to the BTB is not discussed.
This is not persuasive to overcome the rejection. A BTB operates by creating entries therein as branch instructions are encountered during program execution. When a hint instruction is encountered, it will create an entry, which is written to with an output, in the writeback stage. This is done for a branch indicating CS.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183
Prosecution Insights