DETAILED ACTION
Election/Restrictions
Applicant's election with traverse of Species 1 in the reply filed on 7/20/26 is acknowledged. The traversal is on the ground(s) that there is no serious burden because the species have common elements resulting in the species being similarly classified. This is not found persuasive because, as detailed in the restriction, a serious burden does exist because at least the following reason(s) apply: they have a separate status in the art based upon their separate inventive efforts; and/or they have different search queries based upon their different elements or limitations. Classification is not the only cause of serious burden.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 7-11, and 17 is/are rejected under 35 U.S.C. 102a1 as being clearly anticipated by Hsu et al., US 10,276,526.
Regarding claim 1, Hsu (figures 4B & 1G) teaches a semiconductor package of a package-in-package type, the semiconductor package comprising:
a package redistribution layer 402 including a plurality of package redistribution patterns and a package redistribution insulating layer 406 surrounding the plurality of package redistribution patterns (404 & column 7, lines 58-60);
a plurality of electronic components 100 apart from each other in a horizontal direction on the package redistribution layer 402, the plurality of electronic components 100 include a sub package 100;
a package molding layer 412 covering a top surface of the package redistribution layer 402 and surrounding the plurality of electronic components 100; and
a plurality of package connection terminals ( at 410) attached to a bottom surface of the package redistribution layer 402 in a fan-out manner,
the sub package 100 includes a package substrate 114 corresponding to a printed circuit board, a semiconductor chip 106 attached to the package substrate 114, and a sub molding layer 112 on the package substrate 114,
the package substrate 114 includes a base insulating layer 116, package upper pads 120 on a top surface of the base insulating layer 114 and package lower pads 122 on a bottom surface of the base insulating layer 114,
the semiconductor chip 106 includes a plurality of chip pads 102 electrically connected to the package upper pads 120,
the sub molding layer 112 covers the semiconductor chip 106, and
the package lower pads 122 are respectively in contact with (through 128/130) and electrically connected to the plurality of package redistribution patterns (at 408).
In claim 7, Hsu (figures 4B & 1G) teaches the plurality of electronic components 100 further include an electronic device,
the electronic device includes a component substrate 106 and a plurality of component pads 102’ attached to a bottom surface of the component substrate 106,
the package redistribution insulating layer 406 covers the bottom surface of the component substrate 106 and does not cover a side surface of the component substrate 106, and
the package molding layer 112 entirely covers the side surface of the component substrate 106.
Regarding claim 8, Hsu (figures 4B & 1G) teaches the package redistribution insulating layer 406 covers side surfaces of each of the plurality of component pads 102’ and bottom surfaces of each of the plurality of component pads 102’.
With respect to claim 9, Hsu (figures 4B & 1G) teaches
the plurality of electronic components 100 further include an electronic device 106,
the electronic device 106 includes a component body 106 and a plurality of component pads 102’ at a bottom of the component body 106,
the package redistribution insulating layer 406 covers a bottom surface of the component body 106 but not a side surface of the component body 106,
the package molding layer 112 covers the side surface of the component body 106, and
a top surface of the package redistribution insulating layer 406, the bottom surface of the component body 106 , and a bottom surface of each of the plurality of component pads 102’ are at a same vertical level.
As to claim 10, Hsu (figures 4B & 1G) teaches the package redistribution insulating layer 406 covers a lower side surface of the package substrate 114, and the package molding layer 112 covers an upper side surface of the package substrate 114.
In re claim 11, Hsu (figures 4B & 1G) teaches a semiconductor package of a package-in-package type, the semiconductor package comprising:
a package redistribution layer 402 including a plurality of package redistribution patterns and a package redistribution insulating layer surrounding the plurality of package redistribution patterns (column 7, lines 58-60);
a plurality of sub packages 100 apart from each other in a horizontal direction on the package redistribution layer 402, the plurality of sub packages 100 including two sub packages apart from each other in the horizontal direction on the package redistribution layer 402;
a package molding layer 412 covering a top surface of the package redistribution layer 402 and surrounding the plurality of sub packages 100; and
a plurality of package connection terminals 410 attached to a bottom surface of the package redistribution layer 402 in a fan-out manner, wherein
each sub package 100 of the plurality of sub packages includes a package substrate 114, a semiconductor chip 106 attached to the package substrate 114, and a sub molding layer 112 on the package substrate 114,
the package substrate 114 includes a base insulating layer 116, package upper pads 120 on a top surface of the base insulating layer 116, package lower pads 122 on a bottom surface of the base insulating layer 116, and a bottom solder resist layer (116 enclosing 122), the bottom solder resist layer (116 enclosing 122) covers the bottom surface of the base insulating layer 116 and does not cover the package lower pads 122,
the semiconductor chip 106 includes a plurality of chip pads 102 electrically connected to the package upper pads 120,
the sub molding layer 112 covers the semiconductor chip 106,
the package lower pads 122 are respectively in contact with and electrically connected to the plurality of package redistribution patterns (in 402-column 7, lines 58-60), and
a portion of each of the package lower pads 122 is in contact with (through 128/130) the package redistribution insulating layer 406.
Concerning claim 17, Hsu (figures 4B & 1G) teaches the package redistribution insulating layer (in 406) covers a lower side surface of the package substrate 114, and the package molding layer 412 covers an upper side surface of the package substrate 114.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2-6, and 12-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al., US 10,276,526, as applied to claims 1 and 11 above.
With respect to claims 2 and 12, though Hsu fails to specifically teach the plurality of package redistribution patterns include a plurality of package redistribution line patterns, a plurality of package redistribution vias, and a plurality of package redistribution seed layers, the plurality of package redistribution line patterns are on at least one of a top surface 408 of the package redistribution insulating layer and a bottom surface of the package redistribution insulating layer, the plurality of package redistribution vias passing through the package redistribution insulating layer and are respectively connected to some of the plurality of package redistribution line patterns, the plurality of package redistribution seed layers cover the plurality of package redistribution line patterns and the plurality of package redistribution vias, and the package lower pads are respectively connected to the plurality of package redistribution vias, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this configuration in the invention of Hsu because it is a conventionally known and used package redistribution configuration. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
As to claim 3, though Hsu fails to specifically teach some of the plurality of package redistribution seed layers are respectively between the package lower pads and the plurality of package redistribution vias, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this configuration in the invention of Hsu because it is a conventionally known and used configuration. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
In re claim 4, though Hsu fails to specifically teach a first portion of each of the package lower pads 410 is in contact with the package redistribution insulating layer, and a second portion of each of the package lower pads is in contact with a corresponding one of the plurality of package redistribution seed layers, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this configuration in the invention of Hsu because it is a conventionally known and used configuration. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Concerning claim 5, though Hsu fails to specifically teach the package substrate further includes a bottom solder resist layer, the bottom solder resist layer covers the bottom surface of the base insulating layer and does not cover the package lower pads, a package cavity is defined by the bottom solder resist layer and is between a bottommost end of the bottom solder resist layer and a bottom surface of one of the package lower pads, and the package cavity is completely filled with a portion of one of the plurality of package redistribution vias, a portion of one of the plurality of package redistribution seed layers, and a portion of the package redistribution insulating layer, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this configuration in the invention of Hsu because it is a conventionally known and used configuration. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
Pertaining to claim 6, though Hsu fails to specifically teach the plurality of package redistribution line patterns include a corresponding package redistribution line pattern, the plurality of package redistribution vias include a corresponding package redistribution via, the corresponding package redistribution line pattern forms an integral body with the corresponding package redistribution via, the corresponding package redistribution via extends from a top surface of the corresponding package redistribution line pattern, the plurality of package redistribution seed layers include a corresponding package redistribution seed layer, and the corresponding package redistribution seed layer covers a top surface of the corresponding package redistribution line pattern, a side surface of the corresponding package redistribution via, and a top surface of the corresponding package redistribution via, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this configuration in the invention of Hsu because it is a conventionally known and used configuration. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
In claim 13, Hsu (figures 4B & 1G) teaches a plurality of package cavities (filled by 118) are defined by the bottom solder resist layer (116 covering 122) between bottommost ends of the bottom solder resistive layer (116 covering 122) and bottom surfaces of the package lower pads 122, portions of the plurality of package redistribution vias 118 extend into the plurality of package cavities (filled by 118) from a corresponding one of the plurality of package redistribution patterns (at 408) and are connected respectively to the package lower pads 122, and the corresponding one of the plurality of package redistribution patterns (at 408) is connected to each of the plurality of package redistribution vias 118 (through 126).
Regarding claim 14, though Hsu fails to teach a material of the plurality of package redistribution seed layers is different than a material of the plurality of package redistribution vias and a material of the package lower pads, and a portion of each of the plurality of package redistribution seed layers is between one of the package lower pads and one of the plurality of package redistribution vias respectively connected to the package lower pads, it would have been obvious to one of ordinary skill in the art at the time of the invention to use seed layers in the invention of Hsu because they are conventionally known and used in the art. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07). Further, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the material used for the various sed layers through routine experimentation (MPEP 2144.05).
With respect to claim 15, though Hsu fails to teach one of the plurality of package redistribution line patterns forms an integral body with a package redistribution via in contact with a top surface of the one of the package redistribution line patterns among the plurality of package redistribution vias, it would have been obvious to one of ordinary skill in the art at the time of the invention to use this configuration in the invention of Hsu because it is conventionally known and used in the art. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
As to 16, though Hsu fails to teach each of the plurality of package redistribution vias has a tapered shape having a horizontal width decreasing away from the one of the plurality of package redistribution line patterns that is integral with each of the plurality of package redistribution vias, it would have been obvious to one of ordinary skill in the art at the time of the invention to use tapered vias in the invention of Hsu because they are a conventionally known and sued equivalent via shape. The substitution of one known equivalent technique for another may be obvious even if the prior art does not expressly suggest the substitution (Ex parte Novak 16 USPQ 2d 2041 (BPAI 1989); In re Mostovych 144 USPQ 38 (CCPA 1964); In re Leshin 125 USPQ 416 (CCPA 1960); Graver Tank & Manufacturing Co. V. Linde Air Products Co. 85 USPQ 328 (USSC 1950).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited prior art teach various aspects of the claimed invention.
Any inquiry should be directed to DAVID A ZARNEKE at (571)272-1937. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matt Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAVID A ZARNEKE/Primary Examiner, Art Unit 2891 8/21/26
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