Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-18 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Chiu et al. (hereinafter Chiu, US 2023/0352395).
In regards to independent claim 1, Chiu teaches a semiconductor die, comprising:
a metallization layer extending in a first direction (Chiu, 116), comprising:
a first dielectric layer comprising a first via extending in a second direction (Chiu, 112, 148); and
a metal layer adjacent to the first dielectric layer (Chiu, 116), comprising:
a resistive metal coupled to the first via (Chiu, [0027], Specification of the this application states that TiN meets the definition of a resistive metal).
In regards to dependent claim 2, Chiu teaches the semiconductor die of claim 1, wherein:
the first dielectric layer further comprises: a second via (Chiu, Fig. 1M via to the left of 148); and
the metal layer further comprises:
one or more metal interconnects coupled to the second via (Chiu, Fig. 1M, 116 connected to left via).
In regards to dependent claim 3, Chiu teaches the semiconductor die of claim 1, wherein:
the resistive metal has a first surface (Chiu, Fig. 1M, 116 bottom).
the metal layer comprises:
a second dielectric layer (Chiu, 108); and
a first etch stop layer between the first surface of the resistive metal and the second dielectric layer (Chiu 110).
In regards to dependent claim 4, Chiu teaches the semiconductor die of claim 3, wherein:
the resistive metal has a second surface (Chiu, Fig. 1M, 116 top); and
the semiconductor die further comprises:
a second etch stop layer between the second surface of the resistive metal and the first dielectric layer (Chiu, 130).
In regards to dependent claim 5, Chiu teaches the semiconductor die of claim 4, wherein:
the first etch stop layer comprises silicon carbon nitride (SiCN) (Chiu, [0022]); and
the second etch stop layer comprises SiCN (Chiu, [0029]).
In regards to dependent claim 6, Chiu teaches the semiconductor die of claim 4, wherein the resistive metal comprises titanium nitride (TiN) (Chiu, [0027], Specification of the this application states that TiN meets the definition of a resistive metal).
In regards to dependent claim 7, Chiu teaches the semiconductor die of claim 1, integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter (Chiu, [0001]).
In regards to independent claim 8, Chiu teaches a method of fabricating a metallization layer in a semiconductor die, the metallization layer extending in a first direction comprising:
fabricating a first dielectric layer comprising a first via extending in a second direction (Chiu, [0023]);
fabricating a metal layer adjacent to the first dielectric layer, comprising a resistive metal (Chiu, [0026]); and
coupling the resistive metal to the first via (Chiu, [49]).
In regards to dependent claim 9, Chiu teaches the method of claim 8, wherein:
fabricating the first dielectric layer further comprises:
fabricating a second via (Chiu, [0044]).;
fabricating the metal layer further comprises:
fabricating a metal interconnect (Chiu, [0049]).; and
the method further comprises:
coupling to the second via to the metal interconnect (Chiu, [0052]).
In regards to dependent claim 10, Chiu teaches the method of claim 8, wherein:
the resistive metal has a first surface; and
fabricating the metal layer further comprises:
fabricating a second dielectric layer (Chiu, [0023]); and
fabricating a first etch stop layer between the first surface of the resistive metal and the second dielectric layer (Chiu, [0029]).
In regards to dependent claim 11, Chiu teaches the method of claim 10, wherein:
the resistive metal has a second surface; and fabricating the metal layer further comprises (Chiu, [0026]):
fabricating a second etch stop layer between the second surface of the resistive metal and the first dielectric layer (Chiu, [0022]).
In regards to dependent claim 12, Chiu teaches the method of claim 11, wherein:
the first etch stop layer comprises silicon carbon nitride (SiCN) (Chiu, [0022]); and
the second etch stop layer comprises SiCN (Chiu, [0029]).
In regards to dependent claim 13, Chiu teaches the method of claim 11, wherein the resistive metal comprises titanium nitride (TiN) (Chiu, [0027]).
In regards to dependent claim 14, Chiu teaches the method of claim 8, wherein the metal layer comprises a second dielectric layer, wherein fabricating the metal layer further comprises:
depositing a first etch stop layer adjacent to the second dielectric layer (Chiu, [0022]).;
depositing the resistive metal adjacent to the first etch stop layer (Chiu, [0026]); and
depositing a second etch stop layer adjacent to the resistive metal (Chiu, [0029]).
In regards to dependent claim 15, Chiu teaches the method of claim 14, wherein fabricating the metal layer further comprises:
patterning the metal layer to remove excess etch stop from the first etch stop layer and excess etch stop from the second etch stop layer whereby the first etch stop layer remains adjacent to a first surface of the resistive metal and the second etch stop layer remains adjacent to a second surface of the resistive metal (Chiu, Fig. 1J), 1130, 110).
In regards to dependent claim 16, Chiu teaches the method of claim 15, wherein fabricating the first dielectric layer further comprises:
etching the first dielectric layer to the second etch stop layer to begin formation of the first via (Chiu, 0025]).
In regards to dependent claim 17, Chiu teaches the method of claim 16, wherein fabricating the first dielectric layer further comprises:
etching the second etch stop layer to expose the second surface of the resistive metal (Chiu, [0044]).
In regards to dependent claim 18, Chiu teaches the method of claim 17, further comprising:
depositing metal into the first via (Chiu, [0049]).
Conclusion
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/WILLIAM C TRAPANESE/Primary Examiner, Art Unit 2812
