Prosecution Insights
Last updated: October 27, 2026

William C Trapanese, USPTO Patent Examiner

Listed by the USPTO as TRAPANESE, WILLIAM C

Tech Center 2800 • Art Units: 2171 2812 2826

This examiner grants 78% of resolved cases

Analysis

TRAPANESE, WILLIAM C is assigned to tech center 2800 and art unit 2171. The record includes 668 resolved cases, an allowance rate of 77.5%, and a median of 1157 days to allowance. The volume supports using the profile as a meaningful prosecution reference, while the timing figure should inform expectations for portfolio management.

The interview lift is 20.6%, indicating a potential benefit from interviews when they are directed to concrete examination issues. The listed companies are Samsung Electronics Co., Ltd., SanDisk Technologies Inc., and Samsung Display Co., Ltd. The listed firms are DORITY & MANNING, P.A., FENWICK & WEST LLP, and HARNESS DICKEY (DETROIT). These organizations identify representative participants in the available record.

Written from this page's own data; every figure is computed from USPTO records and verified before publication.

Performance Statistics

77.5%
Allow Rate
+9.5% vs TC avg
687
Total Applications
+20.6%
Interview Lift
1157
Avg Prosecution Days
Based on 668 resolved cases, 2023–2026

Rejection Statute Breakdown

11.9%
§101 Eligibility
23.3%
§102 Novelty
56.9%
§103 Obviousness
2.6%
§112 Clarity

Currently Pending Office Actions

App #TitleStatusAssignee
18653157 INTEGRATED CIRCUIT MEMORY DEVICES HAVING HIGHLY INTEGRATED MEMORY CELLS THEREIN WITH ENHANCED LANDING PAD STRUCTURES Non-Final OA Samsung Electronics Co., Ltd.
18650189 SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME Non-Final OA SAMSUNG ELECTRONICS CO., LTD.
18426365 DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME Non-Final OA Samsung Display Co., Ltd.
18544605 QUANTUM DEVICE Non-Final OA NEC Corporation
18750011 ELECTRONIC DEVICE COMPRISING A LAYER OF 2D MATERIAL Non-Final OA Commissariat à l'Énergie Atomique et aux Énergies Alternatives
18665944 SEMICONDUCTOR DIE HAVING A METALLIZATION LAYER INCLUDING A METAL LAYER AND A RESISTIVE METAL IN THE METAL LAYER TO DECREASE PARASITIC CAPACITANCE Non-Final OA QUALCOMM Incorporated
18692926 METHOD FOR PRODUCING HETEROEPITAXIAL WAFER Non-Final OA SHIN-ETSU HANDOTAI CO., LTD.
18426069 THREE-DIMENSIONAL MEMORY DEVICE WITH COMPACT STAIRCASES AND METHODS OF FORMING THE SAME Non-Final OA SANDISK TECHNOLOGIES LLC
18426040 THREE-DIMENSIONAL MEMORY DEVICE WITH COMPACT STAIRCASES AND METHODS OF FORMING THE SAME Non-Final OA SANDISK TECHNOLOGIES LLC
18675186 LAYOUT OF STATIC RANDOM ACCESS MEMORY Non-Final OA UNITED MICROELECTRONICS CORP.

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Frequently Asked Questions

What is examiner William C Trapanese's allowance rate?

77.5% of resolved applications examined by William C Trapanese were allowed (668 resolved cases), compared with 56.1% across Art Unit 2171 over the last five years.

Does an interview help with examiner William C Trapanese?

This examiner's interview lift is +20.6 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.

How long does examiner William C Trapanese take to allow a patent?

Applications allowed by William C Trapanese took 1,157 days on average from filing to allowance.

Which art unit does examiner William C Trapanese work in?

William C Trapanese examines applications in Art Unit 2171 in Tech Center 2800 (Semiconductors, Circuits & Optics).

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