DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 8/16/2024 and 4/2/2025 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
The abstract and title are consistent with the requirements set forth in the MPEP 608.01(b) and 606, respectively. Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8, 14, 16 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Iwasaki et al. US PGPub. 2013/0032914. Regarding claim 1, Iwasaki teaches a solid-state imaging device (fig. 19) [0211], comprising: a semiconductor substrate (101, fig. 19) [0062] that includes a light-receiving element (pixel PX including photodiodes and transistors) [0079]; an on-chip lens (ML, fig. 19) [0063] on the semiconductor substrate (101); and a glass substrate (301, fig. 19) [0120] spaced apart (spaced apart by layers 501 and 110, fig. 19) from the on-chip lens (ML) on the semiconductor substrate (101), wherein the glass substrate (301) includes a first trench (TR, fig. 19; hereinafter called 601TR; see examiner’s fig. 1) in a (bottom) surface that faces the semiconductor substrate (101) (Iwasaki et al., fig. 19).
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Examiner’s Fig. 1
Regarding claim 2, Iwasaki teaches the solid-state imaging device according to claim 1, further comprising a resin layer (110, fig. 19; made of silicon or siloxane resin) [0206] on the on-chip lens (ML), wherein the on-chip lens (ML) is on a first (top) surface of the semiconductor substrate (101), the glass substrate (301) is on a (top) side of the first (top) surface of the semiconductor substrate (101), and the glass substrate (301) is spaced apart (spaced apart by adhesive layer 501) from the resin layer (110) (Iwasaki et al., fig. 19). Regarding claim 3, Iwasaki teaches the solid-state imaging device according to claim 2, further comprising a structure in one of a pillar shape or a wall shape (601P, see examiner’s fig. 1), wherein the structure (601P) supports (protrudes downwards) the glass substrate (301) against the semiconductor substrate (101) (Iwasaki et al., fig. 19). Regarding claim 4, Iwasaki teaches the solid-state imaging device according to claim 3, wherein: the semiconductor substrate (101) further includes a plurality of light-receiving elements (PX) in a matrix (fig. 3 and 19) [0079] on the (top) side of the first (top) surface of the semiconductor substrate (101), the plurality of light-receiving elements (PX) includes the light-receiving element (PX), and the structure (601P) is at a boundary part of neighboring light-receiving elements (PX) of the plurality of light-receiving elements (PX) (Iwasaki et al., fig. 19). Regarding claim 5, Iwasaki teaches the solid-state imaging device according to claim 3, wherein the structure (601p) divides the first trench (601TR) into a plurality of second trenches (601TR) (Iwasaki et al., fig. 19). Regarding claim 6, Iwasaki teaches the solid-state imaging device according to claim 3, wherein the structure (601P) is a partition wall that is a part of the glass substrate (301), and the structure (601P) divides the first trench (601TR) into a plurality of second trenches (601TR) (Iwasaki et al., fig. 19). Regarding claim 7, Iwasaki teaches the solid-state imaging device according to claim 4, wherein: the on-chip lens (ML) corresponds one-to-one to each of the plurality of light-receiving elements (PX), the structure (601P) divides the first trench (601TR) into a plurality of second trenches (601TR), and each of the plurality of second trenches (601TR) corresponds one-to-one to the on-chip lens (ML) (Iwasaki et al., fig. 19). Regarding claim 8, Iwasaki teaches the solid-state imaging device according to claim 3, further comprising a plurality of on-chip lenses (ML) that includes the on-chip lens (ML), wherein: the structure (601P) divides the first trench (601TR) into a plurality of second trenches (601TR), and each of the plurality of second trenches (601TR) corresponds one-to-one to each of the plurality of on-chip lenses (ML) (Iwasaki et al., fig. 19). Regarding claim 14, Iwasaki teaches the solid-state imaging device according to claim 2, wherein a roughness (grating 601, fig. 19) [0121] of the (bottom) surface of the glass substrate (301) which faces the semiconductor substrate (101) is higher than a roughness (flat, no grating, fig. 19) of a (top) surface, of the glass substrate (301), opposite to the first (top) surface of the semiconductor substrate (101) (Iwasaki et al., fig. 19). Regarding claim 16, Iwasaki teaches the solid-state imaging device according to claim 5, wherein a cross-sectional shape of a surface of the plurality of second trenches (601TR) which is parallel to the first surface is one of a rectangle or a circle (Iwasaki et al., fig. 19). Regarding claim 20, Iwasaki teaches an electronic apparatus (40, fig. 1) [0050], comprising: a solid-state imaging device (1, fig. 1) [0050]; an optical system (42, fig. 1) [0050] configured to image incident light on a light-receiving surface of the solid-state imaging device (1); and a processor (44, fig. 1) [0050] configured to control the solid-state imaging device (1), wherein the solid-state imaging device (1, fig. 1 and fig. 19) includes: a semiconductor substrate (101, fig. 19) [0062] that includes a light-receiving element (pixel PX including photodiodes and transistors) [0079]; an on-chip lens (ML, fig. 19) [0063] on the semiconductor substrate (101); and a glass substrate (301, fig. 19) [0120] spaced apart (spaced apart by layers 501 and 110, fig. 19) from the on-chip lens (ML) on the semiconductor substrate (101), wherein the glass substrate (301) includes a trench (TR, fig. 19; hereinafter called 601TR; see examiner’s fig. 1) in a (bottom) surface that faces the semiconductor substrate (101) (Iwasaki et al., fig. 19).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Iwasaki et al. US PGPub. 2013/0032914. Regarding claim 9, Iwasaki teaches the solid-state imaging device according to claim 1, wherein a depth of the first trench (601TR) is significantly less than a maximum thickness of the glass substrate (301) but fails indicated that the drawings are to scale, or to be specific regarding wherein a depth of the first trench is: one of equal to or greater than 1µm (micrometer), and equal to or less than half a maximum thickness of the glass substrate (301). However, at the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in art to use a depth of the trench such that equal to or less than half a maximum thickness of the glass substrate in the range as claimed, because it has been held that where the general conditions (fig. 19 already shows first trench (601TR) is significantly less than a maximum thickness of the glass substrate (301)) of the claims are discloses in the prior art, it is not inventive to discover the optimum or workable range by routine experimentation. See MPEP 2144.05.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Iwasaki et al. US PGPub. 2013/0032914 as applied to claim 1 above, and further in view of Goto et al. US PGPub. 2019/0109161.
Regarding claim 12, Iwasaki does not teach the solid-state imaging device according to claim 1, further comprising an antireflection film on a (top) surface, of the glass substrate (301), opposite to the (bottom) surface that faces the semiconductor substrate (101). However, Goto teaches a solid-state imaging device (50, fig. 5) [0197] comprising an antireflection film (36, fig. 5) [0204] on a (top) surface, of the glass substrate (42, fig. 5) [0230], opposite to the (bottom) surface that faces the semiconductor substrate (12, fig. 5)[0069] (Goto et al., fig. 5). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to add an antireflection layer on the glass substrate of Iwasaki in the manner as taught by Goto because antireflective layers are well known in the art and such material/structure is art recognized and suitable for the intended purpose of reducing the difference in refractive index between air and the top layer of the glass substrate to prevent light incident on the imaging device from being reflected from the interface and generating noise (Goto et al., [0204]) (see MPEP 2144.07). Regarding claim 13, Iwasaki does not teach the solid-state imaging device according to claim 1, further comprising a filter on a (top) surface, of the glass substrate (301), opposite to the (bottom) surface that faces the semiconductor substrate (101), wherein the filter is configured to absorb infrared light.
However, Goto teaches a solid-state imaging device (50, fig. 5) [0197] comprising a filter (34, fig. 5) [0105] on a (top) surface, of the glass substrate (42, fig. 5) [0230], opposite to the (bottom) surface that faces the semiconductor substrate (12, fig. 5)[0069], wherein the filter (34) is configured to absorb infrared light [0105] (Goto et al., fig. 5).
At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to add an infrared absorbing layer on the glass substrate of Iwasaki in the manner as taught by Goto because infrared absorbing layers are well known in the art and such material/structure is art recognized and suitable for the intended purpose of reducing the difference in refractive index between air and the top layer of the glass substrate to reduce noise generated by infrared light (Goto et al., [0008]) (see MPEP 2144.07).
Allowable Subject Matter
Claims 10-11 and 15 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and the double patenting rejections overcome.
The following is an examiner’s statement of reasons for allowance: the prior arts of record taken alone or in combination neither anticipates nor renders obvious the a solid-state imaging device comprising “a first light-shielding film on a surface of the structure on the side of the semiconductor substrate” as recited in claim 10 and in combination with the rest of the limitations recited in claims 1-3; and a solid-state imaging device wherein “the resin layer rises toward an inside of each of the plurality of second trenches” as recited in claim 15 in combination with the rest of the limitations of claims 1-3 and 5. Claim 11 is also objected to as allowable for further limiting and depending upon allowable claim 10. Claims 17-19 are allowable if double patenting rejections overcome by timely filing a terminal disclaimer.
The following is an examiner’s statement of reasons for allowance: the prior arts of record taken alone or in combination neither anticipates nor renders obvious a solid-state imaging device comprising “a glass substrate spaced apart from the on-chip lens; a structure in one of a pillar shape or a wall shape, wherein the structure supports the glass substrate against the semiconductor substrate; and a first light-shielding film on a surface of the structure on a side of the semiconductor substrate” as recited in claim 17.
Claims 18-19 are also allowed for further limiting and depending upon allowed claim 17.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-16 of U.S. Patent No. 12,009,377. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of the current application is broader than and anticipated by claim 1 of patent no. 12,009,377. Claims 2-16 are similar and therefore anticipated or at least obvious over claims 2-16 of patent no. 12,009,377. Claim 2 (1-2) is similar to claim 1 of patent no. 12,009,377. Claims 17-19 of the current application is similar to the combination of claim 1+2+12, 13 and 7, respectively of patent no. 12,009,377. See table 1 below for claim to claim matching and comparison. Claim 20 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 19 of U.S. Patent No. 12,009,377 in view of Iwasaki et al. US PGPub. 2013/0032914. Regarding claim 20 of the current application, claim 19 of patent no. 12,009,377 recites most of the limitation except “wherein the glass substrate includes a trench in a surface that faces the semiconductor substrate.” See table 1 below for claim matching. However, Iwasaki teaches a solid-state imaging device (fig. 19) [0211], comprising wherein the glass substrate (301, fig. 19) [0120] includes a first trench (TR, fig. 19; hereinafter called 601TR; see examiner’s fig. 1) in a (bottom) surface that faces the semiconductor substrate (101, fig. 19) [0062] (Iwasaki et al., fig. 19). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the solid state imaging device in the electronic apparatus of claim 19 of patent no. 12,009,377 by having the trench in a surface of the glass substrate that faces the semiconductor substrate as recited in claim 20 of the current application because such trenches are well known in the art and such material/structure is art recognized and suitable for the intended purpose of diffracting thereby reducing the intensity of light re-incident on the pixel to suppress deterioration of the image quality (Iwasaki et al., [0142] and [0150]) (see MPEP 2144.07).
Current Application
Patent No. 12,009,377
1. A solid-state imaging device, comprising: a semiconductor substrate that includes a light-receiving element; an on-chip lens on the semiconductor substrate; and a glass substrate spaced apart from the on-chip lens on the semiconductor substrate, wherein the glass substrate includes a first trench in a surface that faces the semiconductor substrate.
2. The solid-state imaging device according to claim 1, further comprising a resin layer on the on-chip lens, wherein the on-chip lens is on a first surface of the semiconductor substrate, the glass substrate is on a side of the first surface of the semiconductor substrate, and the glass substrate is spaced apart from the resin layer.
1. A solid-state imaging device, comprising: a semiconductor substrate including a light-receiving element; an on-chip lens disposed on a first surface of the semiconductor substrate; a resin layer that covers the on-chip lens; and a glass substrate disposed on a side of the first surface of the semiconductor substrate separately from the resin layer, wherein the glass substrate includes a first trench in a surface that faces the semiconductor substrate.
3. The solid-state imaging device according to claim 2, further comprising a structure in one of a pillar shape or a wall shape, wherein the structure supports the glass substrate against the semiconductor substrate.
2. The solid-state imaging device according to claim 1, further comprising a structure in a wall shape which supports the glass substrate against the semiconductor substrate
4. The solid-state imaging device according to claim 3, wherein: the semiconductor substrate further includes a plurality of light-receiving elements in a matrix on the side of the first surface of the semiconductor substrate, the plurality of light-receiving elements includes the light-receiving element, and the structure is at a boundary part of neighboring light-receiving elements of the plurality of light-receiving elements.
3. The solid-state imaging device according to claim 2, wherein: the semiconductor substrate further includes a plurality of light-receiving elements, including the light-receiving element, disposed in a matrix form on the side of the first surface of the semiconductor substrate, and the structure is disposed at a boundary part of neighboring light-receiving elements of the plurality of light-receiving elements.
5. The solid-state imaging device according to claim 3, wherein the structure divides the first trench into a plurality of second trenches.
4. The solid-state imaging device according to claim 3, wherein the structure divides the first trench into a plurality of second trenches.
6. The solid-state imaging device according to claim 3, wherein the structure is a partition wall that is a part of the glass substrate, and the structure divides the first trench into a plurality of second trenches.
5. The solid-state imaging device according to claim 4, wherein the structure is a partition wall that is a part of the glass substrate and divides the first trench into the plurality of second trenches.
7. The solid-state imaging device according to claim 4, wherein: the on-chip lens corresponds one-to-one to each of the plurality of light-receiving elements, the structure divides the first trench into a plurality of second trenches, and each of the plurality of second trenches corresponds one-to-one to the on-chip lens.
6. The solid-state imaging device according to claim 4, wherein: the on-chip lens corresponds one-to-one to each of the plurality of light-receiving elements, and the structure divides the first trench into the plurality of second trenches such that each of the plurality of second trenches corresponds one-to-one to the on-chip lens.
8. The solid-state imaging device according to claim 3, further comprising a plurality of on-chip lenses that includes the on-chip lens, wherein: the structure divides the first trench into a plurality of second trenches, and each of the plurality of second trenches corresponds one-to-one to each of the plurality of on-chip lenses.
7. The solid-state imaging device according to claim 4, wherein: the on-chip lens corresponds one-to-one to each of the plurality of light-receiving elements, the structure divides the first trench into the plurality of second trenches such that each of the plurality of second trenches corresponds one-to-one to each of a plurality of on-chip lenses that includes the on-chip lens.
9. The solid-state imaging device according to claim 1, wherein a depth of the first trench is: one of equal to or greater than 1µm (micrometer), and equal to or less than half a maximum thickness of the glass substrate.
8. The solid-state imaging device according to claim 4, wherein a depth of the first trench is equal to or greater than 1µm (micrometer) and is a depth equal to or less than half a maximum thickness of the glass substrate.
10. The solid-state imaging device according to claim 3, further comprising a first light-shielding film on a surface of the structure on the side of the semiconductor substrate.
12. The solid-state imaging device according to claim 2, further comprising a first light-shielding film provided on a surface of the structure on the side of the semiconductor substrate.
11. The solid-state imaging device according to claim 10, further comprising a second light-shielding film on a side of the structure.
13. The solid-state imaging device according to claim 12, further comprising a second light-shielding film provided on a side of the structure.
12. The solid-state imaging device according to claim 1, further comprising an antireflection film on a surface, of the glass substrate, opposite to the surface that faces the semiconductor substrate.
14. The solid-state imaging device according to claim 1, further comprising an antireflection film provided on a surface, of the glass substrate, opposite to the surface that faces the semiconductor substrate.
13. The solid-state imaging device according to claim 1, further comprising a filter on a surface, of the glass substrate, opposite to the surface that faces the semiconductor substrate, wherein the filter is configured to absorb infrared light.
15. The solid-state imaging device according to claim 1, further comprising a filter that is provided on a surface, of the glass substrate, opposite to the surface that faces the semiconductor substrate, wherein the filter absorbs infrared light.
14. The solid-state imaging device according to claim 2, wherein a roughness of the surface of the glass substrate which faces the semiconductor substrate is higher than a roughness of a surface, of the glass substrate, opposite to the first surface of the semiconductor substrate.
16. The solid-state imaging device according to claim 1, wherein a roughness of the surface of the glass substrate which faces the semiconductor substrate is higher than a roughness of a surface, of the glass substrate, opposite to the first surface of the semiconductor substrate.
15. The solid-state imaging device according to claim 5, wherein the resin layer rises toward an inside of each of the plurality of second trenches.
9. The solid-state imaging device according to claim 4, wherein the resin layer rises toward an inside of each of the plurality of second trenches.
16. The solid-state imaging device according to claim 5, wherein a cross-sectional shape of a surface of the plurality of second trenches which is parallel to the first surface is one of a rectangle or a circle.
10. The solid-state imaging device according to claim 4, wherein a cross-sectional shape of a surface of the plurality of second trenches which is parallel to the first surface is a rectangle.
11. The solid-state imaging device according to claim 4, wherein a cross-sectional shape of a surface of the plurality of second trenches which is parallel to the first surface is a circle.
17. A solid-state imaging device, comprising: a semiconductor substrate that includes a light-receiving element; an on-chip lens on the semiconductor substrate; a glass substrate spaced apart from the on-chip lens; a structure in one of a pillar shape or a wall shape, wherein the structure supports the glass substrate against the semiconductor substrate; and a first light-shielding film on a surface of the structure on a side of the semiconductor substrate.
1. A solid-state imaging device, comprising: a semiconductor substrate including a light-receiving element; an on-chip lens disposed on a first surface of the semiconductor substrate; a resin layer that covers the on-chip lens; and a glass substrate disposed on a side of the first surface of the semiconductor substrate separately from the resin layer, wherein the glass substrate includes a first trench in a surface that faces the semiconductor substrate.2. The solid-state imaging device according to claim 1, further comprising a structure in a wall shape which supports the glass substrate against the semiconductor substrate.
12. The solid-state imaging device according to claim 2, further comprising a first light-shielding film provided on a surface of the structure on the side of the semiconductor substrate.
18. The solid-state imaging device according to claim 17, further comprising a second light-shielding film on a side of the structure.
13. The solid-state imaging device according to claim 12, further comprising a second light-shielding film provided on a side of the structure.
19. The solid-state imaging device according to claim 17, further comprising: a plurality of light-receiving elements that includes the light-receiving element; and a plurality of pillar-shaped structures, wherein each pillar-shaped structure of the plurality of the pillar-shaped structures corresponds to one of the plurality of light-receiving elements.
7. The solid-state imaging device according to claim 4, wherein: the on-chip lens corresponds one-to-one to each of the plurality of light-receiving elements, the structure divides the first trench into the plurality of second trenches such that each of the plurality of second trenches corresponds one-to-one to each of a plurality of on-chip lenses that includes the on-chip lens.
20. An electronic apparatus, comprising: a solid-state imaging device; an optical system configured to image incident light on a light-receiving surface of the solid-state imaging device; and a processor configured to control the solid-state imaging device, wherein the solid-state imaging device includes: a semiconductor substrate that includes a light-receiving element; an on-chip lens on the semiconductor substrate; and a glass substrate spaced apart from the on-chip lens on the semiconductor substrate, wherein the glass substrate includes a trench in a surface that faces the semiconductor substrate.
19. An electronic apparatus, comprising: a solid-state imaging device; an optical system configured to image incident light on a light-receiving surface of the solid-state imaging device; and a processor configured to control the solid-state imaging device, wherein the solid-state imaging device includes: a semiconductor substrate including a light-receiving element; an on-chip lens disposed on a first surface of the semiconductor substrate; a resin layer that covers the on-chip lens; a glass substrate disposed on a side of the first surface of the semiconductor substrate separately from the resin layer; a structure in a wall shape that supports the glass substrate against the semiconductor substrate; and a light-shielding film on a surface, of the structure, that is on the side of the semiconductor substrate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NDUKA E OJEH whose telephone number is (571)270-0291. The examiner can normally be reached M-F; 9am - 5pm..
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/NDUKA E OJEH/Primary Examiner, Art Unit 2892