DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 05/16/2024 and 02/10/2025 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Objections
Claim 19 objected to because of the following informalities:
Claim 19, line 2: “a second end of one of the active regions” should read --- the second end of one of the active regions ---
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation "a horizontal direction" in line 2. There is already a prior recitation of both “a first horizontal direction” and “a second horizontal direction” in claim 1, on which claim 6 depends through claim 5 – rendering it unclear if “a horizontal direction” refers to either of the “first horizontal direction” or the “second horizontal direction”, or a different direction. Therefore, for the purposes of Examination, and to distinguish “a horizontal direction” from both of “the first horizontal direction” and “the second horizontal direction”, Examiner has interpreted “a horizontal direction” in line 2 as --- a vertical direction --- however, this edit may be altered if Applicant intends otherwise.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-12 and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bae (U.S. PG Pub No US2022/0181329A1).
Regarding claim 1, Bae teaches a semiconductor device [see figs. 1-4, 0012-0013] comprising:
a substrate (21) fig. 1 [0013] having an active region (AC) fig. 1 [0015];
a gate structure (WL) fig. 1 [0015] (word lines part of gate structure - connected to and acting as extension of gate electrodes [0015-0016, 0028]) on (supported by) the substrate (21), the gate structure (WL) extending across the active region (AC) in a first horizontal direction (“x” direction of annotated fig. 2 below) [0015];
bit line structures (BL, DC) fig. 1 [0015-0016] (DC part of bit line structures in that they attached to and acting as extensions of bit lines BL [see also fig. 3, 0013, 0016]) on bit line trenches (gaps in respective 57’s, filled by respective BL’s, DC’s) fig. 1 [0013, 0024] (see also fig. 4) extending in a second horizontal direction ( “y” direction of annotated fig. 2 below) [0015], intersecting the first horizontal (x) direction, the bit line trenches (gaps in 57s) on (supported by) an upper surface of the substrate (21) across (over) the gate structure (WL) (see figs. 2, fig. 3 perspective for BL extending across WL);
contact plugs (BC) fig. 1 [0015] between (laterally between) the bit line structures (BL, DC);
landing pad structures (71s with respective 69s) fig. 1 [0013, 0060] on the contact plugs (BC); and
an insulating pattern (comprising 57) fig. 1 [0024, 0052] (formed of insulating material like silicon oxide [0052]) between (laterally between) the landing pad structures (71s with respective 69s), the insulating pattern (57) in (direct) contact with the bit line structures (BL, DC) (see also fig. 4), wherein
portions of the bit line structures (BL, DC) extend in the second (y) horizontal direction in the bit line trenches (gaps in respective 57’s, filled by respective BL’s), and
each of the landing pad structures (71s with 69s) includes a lower landing pad (LP of 71 with 69) [see annotated fig. 1 below], arranged on a level lower (partially lower) than that of each of upper surfaces (uppermost surface of 45) fig. 1 [0014] of the bit line structures (BL, DC) (bottommost surface of 69 of LP below uppermost surface of 45 of BL), and an upper landing pad (UP of 71 with 69) [see annotated fig. 1 below] on the lower landing pad (LP).
[AltContent: textbox (x[img-media_image1.png][img-media_image1.png])][AltContent: connector][AltContent: rect][AltContent: rect][AltContent: arrow][AltContent: rect][AltContent: textbox (R2)][AltContent: arrow][AltContent: textbox (R1)][AltContent: rect][AltContent: arrow][AltContent: textbox (LP)][AltContent: arrow][AltContent: textbox (UP)]
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Annotated fig. 1 and fig. 2 of Bae
Regarding claim 2, Bae teaches the semiconductor device [see figs. 1-4, 0012-0013] of claim 1. Bae also teaches wherein a (maximum) horizontal width of each of the upper landing pads (UP) [see annotated fig. 1 above] is (clearly) wider than a (maximum) horizontal width of each of the lower landing pads (LP) [see annotated fig. 1 above], and lower surfaces (LS) (local lower surface LS of UP) of the upper landing pads (UP) overlap upper surfaces (uppermost surface of 45) fig. 1 [0014] of the bit line structures (BL, DC) fig. 1 [0015] in a vertical direction (see annotated fig. 1 of Bae above).
Regarding claim 3, Bae teaches the semiconductor device [see figs. 1-4, 0012-0013] of claim 1. Bae also teaches wherein a horizontal width of each of the upper landing pads (UP) [see annotated fig. 1 above] upwardly decreases (in region R1 of UP, horizontal width of UP decreases from bottom upwards along slope of triangular region R1, as defined in annotated fig. 1 above).
Regarding claim 4, Bae teaches the semiconductor device [see figs. 1-4, 0012-0013] of claim 1. Bae also teaches wherein the lower landing pad (LP) [see annotated fig. 1 above] does not overlap the bit line structures (BL, DC) fig. 1 [0015] in a vertical direction (vertical direction of fig. 1), and a (right) portion of the upper landing pad (UP) overlaps the bit line structures (BL, DC) in the vertical direction.
Regarding claim 5, Bae teaches the semiconductor device [see figs. 1-4, 0012-0013] of claim 1. Bae also teaches wherein the landing pad structures (71s with respective 69s) fig. 1 [0013, 0060] include a first landing pad structure (L1) [see annotated fig. 1-II below] and a second landing pad structure (L2) [see annotated fig. 1-II below], adjacent (nearby) to each other in the first horizontal direction (x/horizontal direction of fig. 1 and fig. 2), with the insulating pattern (57) fig. 1 [0024, 0052] interposed (laterally) therebetween, a first side surface (right) of the insulating pattern (57) is in (thermal) contact with a first lower landing pad (LP1) and a first upper landing pad (UP1) of the first landing pad structure (L1) (57 thermally connected with entirety of 69 with 71), and a second (left) side surface of the insulating pattern (57), opposite to the first (right) side surface, is in (thermal) contact with a second upper landing pad (UP2) of the second landing pad structure (L2) (57 thermally connected with entirety of 69 with 71 through adjoined material) [see annotated fig. 1-II below].
[AltContent: rect][AltContent: rect][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (LP2)][AltContent: textbox (UP2)][AltContent: textbox (UP1)][AltContent: textbox (LP1)][AltContent: arrow][AltContent: arrow][AltContent: textbox (L2)][AltContent: textbox (L1)][AltContent: rect][AltContent: rect]
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Annotated fig. 1-II of Bae
Regarding claim 6, Bae teaches the semiconductor device [see figs. 1-4, 0012-0013] of claim 5. Bae also teaches wherein the first lower landing pad (LP1) annotated fig. 1-II above [0013] and the second upper landing pad (UP2) annotated fig. 1-II above [0013] do not overlap each other in a vertical direction (underlined added for Examination purposes).
Regarding claim 7, Bae teaches the semiconductor device [see figs. 1-4, 0012-0013] of claim 5. Bae also teaches wherein the first lower landing pad (LP1) annotated fig. 1-II above [0013] and the second upper landing pad (UP2) annotated fig. 1-II above [0013] are (at least partially) spaced apart from each other in horizontal and vertical directions.
Regarding claim 8, Bae teaches the semiconductor device [see figs. 1-4, 0012-0013] of claim 1. Bae also teaches further comprising:
a metal-semiconductor compound layer (67) fig. 1 [0013] (metal silicide being formed of metal-silicon semiconductor compound [0013]) between (vertically between) the contact plugs (BC) fig. 1 [0015] and the lower landing pads (LP) (see annotated fig. 1) of the landing pad structures (71s with respective 69s) fig. 1 [0013, 0060], wherein the metal-semiconductor compound layer (67) is on (at) a level lower than that of each of the upper surfaces (uppermost surface of 45) fig. 1 [0014] of the bit line structures (BL, DC) fig. 1 [0015].
Regarding claim 9, Bae teaches the semiconductor device [see figs. 1-4, 0012-0013] of claim 1. Bae also teaches wherein each of the bit line structures (BL, DC) fig. 1 [0015] includes a first conductive layer (43) fig. 1 [0014] in (thermal) contact with the active region (AC) fig. 1 [0015] and a second conductive layer (44) fig. 1 [0014] on the first conductive layer (43), and the first conductive layer (43) includes a metal-semiconductor compound (metal silicide being formed of metal-silicon semiconductor compound [0044]).
Regarding claim 10, Bae teaches the semiconductor device [see figs. 1-4, 0012-0013] of claim 9. Bae also teaches wherein the first conductive layer (43) fig. 1 [0014] is on (supported by/ in) the bit line trench (gaps in respective 57’s, filled by respective BL’s) fig. 1 [0013, 0024] (see also fig. 4).
Regarding claim 11, Bae teaches the semiconductor device [see figs. 1-4, 0012-0013] of claim 1. Bae also teaches wherein a horizontal width of the insulating pattern (comprising 57 with directly attached 78) fig. 1 [0022, 0024, 0052] (formed of insulating materials like silicon oxide [0052] for 57 and SiCN for 78 [0021, 0023]) increases upwardly (horizontal x direction width of 57 with 78 adjoined insulating material increases from location of 57 to location of 78).
Regarding claim 12, Bae teaches the semiconductor device [see figs. 1-4, 0012-0013] of claim 1. Bae also teaches wherein the bit line structures (BL, DC further comprising respective bit line capping structures 49, 52, 55) fig. 1 [0013, 0036, 0039] have upper surfaces (upper surface of 55) having recesses (apparent gap/recess in 55 caused by indentation of 77), respectively, and
the insulating pattern (comprising 57 with directly attached 77, 78) fig. 1 [0022-0024, 0052] (collective insulating pattern formed of insulating materials like silicon oxide [0052] for 57 and SiCN for 78 [0021, 0023] and SiN for 77 [0077]) fills one of the recesses (77 fills apparent recess in 55 – see fig. 1).
Regarding claim 17, Bae teaches a semiconductor device [see figs. 1-4, 0012-0013] comprising:
a substrate (21) fig. 1 [0013] having active regions (AC’s) fig. 1 [0015];
gate structures (WL’s) fig. 1 [0015] (word lines part of gate structure - connected to and acting as extension of gate electrodes [0015-0016, 0028]) on (supported by) the substrate (21), the gate structures (WL’s) extending across the active regions (AC’s) in a first horizontal direction (“x” direction of annotated fig. 2 below) [0015];
bit line structures (BL, DC) fig. 1 [0015-0016] (DC part of bit line structures in that they attached to and acting as extensions of bit lines BL [see also fig. 3, 0013, 0016]) extending across the gate structures (WL’s) in a second horizontal direction (“y” direction of annotated fig. 2 below) [0015], intersecting the first horizontal (x) direction,
a contact plug (BC) fig. 1 [0015] between (laterally between) the bit line structures (BL, DC);
a landing pad structure (71s with respective 69s) fig. 1 [0013, 0060] on the contact plug (BC); and
an insulating pattern (comprising 57) fig. 1 [0024, 0052] (formed of insulating material like silicon oxide [0052]) in (thermal) contact with the bit line structures (BL, DC) and the landing pad structure (71 with 69) (thermally interconnected through adjoined material), wherein
a central portion (midpoint) of each of the active regions (AC) vertically overlaps one of the gate structures (WL) (see annotated fig. 4 perspective for AC’s each overlapping a WL),
a first (bottom) end of each of the active regions (AC) vertically (at least partially) overlaps one of the bit line structures (BL, DC), and a second (top) end of each of the active regions (AC), opposite to the first (bottom) end with respect to the central (midpoint) portion, vertically overlaps the contact plug (BC), and
the landing pad structure (69 with 71) includes a lower landing pad (LP of 71 with 69) [see annotated fig. 1 below], arranged on (at) a level lower (at least partially) than that of each of upper surfaces (uppermost surface of 45) fig. 1 [0014] of the bit line structures (BL, DC) (bottommost surface of 69 lower than uppermost surface of 45), and an upper landing pad (UP of 71 with 69) [see annotated fig. 1 below] on the lower landing pad (LP).
[AltContent: arrow][AltContent: textbox (R1)][AltContent: arrow][AltContent: textbox (LP)][AltContent: arrow][AltContent: textbox (UP)]
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Annotated fig. 1 and fig. 2 of Bae
Regarding claim 18, Bae teaches the semiconductor device [see figs. 1-4, 0012-0013] of claim 17. Bae also teaches wherein
the bit line structures (BL) fig. 1 [0015] include a conductive layer (43) fig. 1 [0014] including a metal-semiconductor compound (43 may comprise metal silicide being formed of metal-silicon semiconductor compound [0044]), and
the conductive layers (43’s of BL’s) are in (thermal) contact with upper surfaces of the first ends (bottoms) of the active regions (AC’s) fig. 1 [0015] (AC and BL thermally interconnected through adjoined material).
Regarding claim 19, Bae teaches the semiconductor device [see figs. 1-4, 0012-0013] of claim 17. Bae also teaches wherein the contact plug (BC) fig. 1 [0015] is in (thermal) contact with an upper surface of the second (top) end of one of the active regions (AC’s) fig. 1 [0015] (AC and BC thermally interconnected through adjoined material).
Regarding claim 20, Bae teaches a semiconductor device [see figs. 1-4, 0012-0013] comprising:
a substrate (21) fig. 1 [0013] having active regions (AC’s) fig. 1 [0015] including a first (bottom of AC) end and a second (top of AC) end;
a gate structure (WL) fig. 1 [0015] (word lines part of gate structure - connected to and acting as extension of gate electrodes [0015-0016, 0028]) on (supported by) the substrate (21), the gate structure (WL) extending across the active regions (AC’s) in a first horizontal direction (“x” direction of annotated fig. 2 below) [0015];
bit line structures (BL, DC) fig. 1 [0015-0016] (DC part of bit line structures in that they attached to and acting as extensions of bit lines BL [see also fig. 3, 0013, 0016]) on bit line trenches (gaps in respective 57’s, filled by respective BL’s, DC’s) fig. 1 [0013, 0024] (see also fig. 4) extending in a second horizontal direction ( “y” direction of annotated fig. 2 below) [0015], intersecting the first horizontal (x) direction, the bit line trenches (gaps in 57s) on (supported by) the first ends (bottoms of AC) across the gate structure (WL);
spacer structures (comprising 57) fig. 1 [0024, 0052] (formed of insulating material like silicon oxide [0052]) on (directly on) side surfaces of bit line structures (BL, DC) (see also fig. 4);
contact plugs (BC) fig. 1 [0015] between the bit line structures, the contact plugs (BC) in (thermal) contact with side surfaces of the spacer structures (57) and lower surfaces of the second ends (top of AC’s) (thermally interconnected through adjoined material);
a metal-semiconductor compound layer (67) fig. 1 [0013] (metal silicide being formed of metal-silicon semiconductor compound [0013]) on the contact plugs (BC);
landing pad structures (71s with respective 69s) fig. 1 [0013, 0060] on (supported by) the metal-semiconductor compound layer (67);
an insulating pattern (49) fig. 1 [0013, 0039] (formed of insulating material like silicon oxide [0039]) between (laterally between) the landing pad structures (71s with 69s), the insulating pattern (49) in (direct) contact with the bit line structures (BL, DC); and
a capacitor structure (95) fig. 1 [0013] on (supported by) the landing pad structures (71s with 69s) and the insulating pattern (49), the capacitor structure (95) electrically connected [0021] (directly connected electrically conductive material between ST and 71) [0014-0015, 0020-0021] to the landing pad structures (69s with 71s), wherein
portions of the bit line structures (BL) extend in the second horizontal (y) direction in the bit line trenches (gaps in 57) (see annotated fig. 2 below; see also fig. 4), and
each of the landing pad structures (69s with 71s) includes a lower landing pad (LP of 71 with 69) [see annotated fig. 1 below], arranged on a level lower than each of upper surfaces of the bit line structures (BL, DC) (bottommost surface of 69 lower than uppermost surface of 45), and an upper landing pad (UP of 71 with 69) [see annotated fig. 1 below] on (supported by) the lower landing pad (LP) (see annotated fig. 1 and fig. 2 below).
[AltContent: arrow][AltContent: textbox (R1)][AltContent: arrow][AltContent: textbox (LP)][AltContent: arrow][AltContent: textbox (UP)]
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Annotated fig. 1 and fig. 2 of Bae
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Bae (U.S. PG Pub No US2022/0181329A1), as applied in claim 1 above, in view of He (U.S. PG Pub No US2021/0082923A1).
Regarding claim 13, Bae teaches the semiconductor device [see figs. 1-4, 0012-0013] of claim 1. However, Bae does not explicitly disclose wherein a horizontal width of each of the bit line structures (comprising BL, DC) fig. 1 [0015-0016] increases upwardly (shown with same horizontal width throughout).
He teaches a semiconductor device [see fig. 2b, 0054-0058] wherein a horizontal width of each of the bit line structures (300 comprising 310) fig. 2B [0054] increases upwardly (horizontal width of 310 portion of 300 vertically increases due to outwardly bulging shape [0060] from lowermost surface to midpoint of circular region, as shown in fig. 2B).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor device of Bae such that the bit line structures further comprise bit line contact structures [0054-0058] with outwardly bulging shapes having variable widths throughout [0060] in order to increase the amount of conductive material associated with the bit line structures [0057-0058] so as to enhance electrical interconnectivity [0057-0058] and reduce contact resistance [0058] of the bit line structures with high manufacturing efficiency [see abstract], as taught by He.
Regarding claim 14, Bae in view of He teaches the semiconductor device [see figs. 1-4, 0012-0013] of claim 13. However, Bae does not explicitly disclose wherein a horizontal width of each of the contact plugs (BC) fig. 1 [0015] decreases upwardly.
He teaches a semiconductor device [see fig. 5, 0116-0121] wherein a horizontal width of each of the contact plugs (310) fig. 5 [0117] decreases upwardly (over tapered trapezoidal shape [0116]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor device of Bae such that the contact plugs are formed to have a tapered trapezoidal shape [0116] with a width continually decreasing from bottom to top [0116-0123] in order to increase the relative contact area of the contact plugs at their bottom surface [0116] for enhanced connections with underlying structures [0116-0119], as taught by He.
Regarding claim 15, Bae in view of He teaches the semiconductor device [see figs. 1-4, 0012-0013] of claim 13. Bae also teaches wherein a horizontal width of the lower landing pad (LP of 71 with 69) [see annotated fig. 1 below] decreases upwardly (in upper portion of region R2 of LP, horizontal width of LP decreases from bottom to top along slope of upper triangular region R2, as defined in close-up of annotated fig. 1 below).
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Close-up of annotated fig. 1 of Bae
Regarding claim 16, Bae in view of He teaches the semiconductor device [see figs. 1-4, 0012-0013] of claim 13. Bae also teaches further comprising:
spacer structures (78) fig. 1 [0014, 0022] on (supported by) side surfaces of the bit line structures (BL, DC) fig. 1 [0015-0016], the spacer structures (78) in (thermal) contact with the contact plugs (BC) fig. 1 [0015] (78, BC thermally connected through adjoined material), wherein each of the spacer structures (78) has a first horizontal width (width of bottommost surface of 78) on (at) a first vertical level (lowermost level of 78), and has a second horizontal width (width of 78 overall at uppermost surface), wider than the first horizontal width (width of 78 at bottommost surface), on a second vertical level (uppermost level of 78) higher than the first vertical level (lowermost level of 78).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form are considered relevant to the present disclosure because they all feature DRAM semiconductor devices with bit line structures, pad structures, plug structures, and gate structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LEX H MALSAWMA/Primary Examiner, Art Unit 2892
/SEAN AYERS WINTERS/Examiner, Art Unit 2892 09/26/2026
Prosecution Insights