DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-13 in the reply filed on 8/21/26 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-9, and 12-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gao et al. (US 2023/0187412, hereinafter, Gao.)
In regard to claims 1 and 8, in fig. 6, Gao discloses a semiconductor device 15 (para [0019]), comprising:
a plurality of dies 1 (para [0018]) stacked in a vertical direction;
a thermal conductive layer 28 (para [0031]) deposited on a top surface of a topmost die 1C (para [0031]);
a base die/interposer 2 (para [0018]) located on a bottom surface of a bottommost die; and
a first contact structure 29 (para [0031]) extending vertically through the plurality of dies,
wherein the first contact structure comprises one or more first channels, each first channel having a first end being in contact with the base die and having a second end being in contact with the thermal conductive layer.
Regarding claims 2 and 9, Gao further comprising a second contact structure 13 (para [0020]) extending vertically inside the plurality of dies, wherein the second contact structure comprises one or more second channels, each second channel extending vertically and being in contact with the base die without contacting the thermal conductive layer. Fig. 6.
Regarding claim 3, wherein the base die comprises a wiring structure including a first wiring structure and a second wiring structure, wherein the first wiring structure is configured to transport heat (described in para [0031]) and the second wiring structure is configured to transmit electronic signals (described in para [0020].)
Regarding claims 6 and 12, wherein each of the first channel and the second channel is a continuous structure along the vertical direction. Fig. 6.
Regarding claims 7 and 13, wherein the second contact structure is surrounded by the first contact structure. Fig. 6.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-5 and 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gao as applied to claim 1 above, and further in view of Li et al. (US 2021/0217734, hereinafter, Li.)
In regard to claims 4-5 and 10-11, Gao discloses all of the claimed limitations as mentioned above, except further comprising: an interposer on a side of the base die opposite to the plurality of dies, wherein the interposer comprises a ball grid array on a side of the interposer opposite to the base dies.
Li, in fig. 1, for example, discloses an analogous semiconductor assembly 100 including stacked dies 103, a thermal layer 110a, a based die 122. Gao further discloses a substrate or interposer 120 with solder devices 125 in order to provide external connections. This is common in the art.
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to include the teaching as taught in order to take the advantage.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN W HA whose telephone number is (571)272-1707. The examiner can normally be reached M-T: 8:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WAEL FAHMY can be reached at (571)-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NATHAN W HA/Primary Examiner, Art Unit 2814
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