DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
In response to a Restriction Requirement mailed on 08/05/2026, the Applicant elected without traverse Group I (claims 1-9 and 20) in a reply filed on 09/29/2026.
Claims 10-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim.
Currently, claims 1-9 and 20 are examined as below.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statements (IDS) filed on 10/28/2024 and 07/27/2026. The IDS have been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
(Marked-Up Version) Semiconductor Devices Including Three-Dimensional Memory Architecture
(Clean Version) Semiconductor Devices Including Three-Dimensional Memory Architecture
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 9 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2020/0411528 A1 to Sung et al. (“Sung”).
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Regarding independent claim 1, Sung in Figs. 1A, 5 and Annotated Fig. 1A teaches a semiconductor device 1000 (Fig. 5, ¶ 12 & ¶ 57-¶ 58, computing system 1000 including DRAMs comprising DRAM cells; Fig. 1A & ¶ 21, memory cell 100 i.e., DRAM cell), comprising vertical transistors 180 (Figs. 1A, 5, ¶ 12, ¶ 21, ¶ 57-¶ 58, transistors 180, as there are multiple memory cells 100 in the device 1000) and storage units 180 (Figs. 1A, 5, ¶ 12, ¶ 21, ¶ 57-¶ 58, capacitors 150, as there are multiple memory cells 100 in the device 1000) coupled with the vertical transistors 180 correspondingly, wherein
the vertical transistor 180 comprises:
a semiconductor layer 182 (Fig. 1A, ¶ 25, semiconductor material 182) comprising a vertical portion 182V (Annotated Fig. 1A) extending in a vertical direction and a first lateral portion 182L1 (Annotated Fig. 1A) extending from a first end (Annotated Fig. 1A, left end) of the vertical portion 182V in a lateral direction, and
a gate structure 104 (Fig. 1A, ¶ 27, conductor 104 having a gate length i.e., gate conductor) coupled to the vertical portion 182V of the semiconductor layer 182 (Annotated Fig. 1A, gate structure 104 and the portion 182V are connected (i.e., coupled) to each other through the layer 184) and extending in the vertical direction (Fig. 1A); and
the first lateral portions 182L1 of the semiconductor layers 182 of two adjacent vertical transistors 180 in the lateral direction are connected with each other (Figs. 1A, 5, Annotated Fig. 1A, the memory cells 100 of the device 1000 must be placed laterally and connect with each other, and the portion 182L1 of the semiconductor layer 182 of each of the memory cells would connect with one another).
Regarding claim 2, Sung in Fig. 1A further teaches the semiconductor layer 182 has a U-shaped cross-section (Fig. 1A) in a plane formed by the vertical direction and the lateral direction (Fig. 1A).
Regarding claim 3, Sung in Fig. 1A and Annotated Fig. 1A further teaches the semiconductor layer 182 of the vertical transistor 180 comprises a second lateral portion 182L2 (Annotated Fig. 1A) extending from a second end (Annotated Fig. 1A, right end) of the vertical portion 182V in the lateral direction, and the second lateral portion 182L2 is coupled with the corresponding storage unit 150 (Fig. 1A, ¶ 25).
Regarding claim 4, Sung in Fig. 1A and Annotated Fig. 1A further teaches the storage unit 150 comprising a capacitor 150 (¶ 25, capacitor 150) with a first electrode 154 (¶ 23, second capacitor electrode 154), a second electrode 152 (¶ 23, first capacitor electrode 152), and a dielectric layer 156 (¶ 23, high-k dielectric 156) between the first electrode 154 and the second electrode 152 (Fig. 1); and
the first electrode 154 is directly coupled with the second lateral portion 182L2 of the semiconductor layer 182 of the corresponding vertical transistor 180 (Annotated Fig. 1A).
Regarding claim 5, Sung in Figs. 1A, 5 and Annotated Fig. 1A further teaches two adjacent vertical transistors 180 in the lateral direction are separated by an isolation structure 110 (Fig. 1A, ¶ 21, third isolation material 110 would separate laterally adjacent transistors 180), and the gate structure 104 of the vertical transistor 180 is positioned in a side (Annotated Fig. 1A, right side) of the vertical portion 182V of the semiconductor layer 182 opposite to the isolation structure 110 (Fig. 1A, the gate structure 104 is coupled to the right side of the semiconductor layer 182, which is opposite to the isolation structure 110 on the left side of the layer 182).
Regarding claim 9, Sung in Fig. 1A further teaches the semiconductor layer 182 has a leakage value lower than a pico-ampere (¶ 26, semiconductor material 182 includes indium gallium zinc oxide, that is the same material for the semiconductor layer as the Applicant purported in paragraph 68 in the specification of the present application, in which such material has a leakage value lower than a pico-ampere).
Regarding independent claim 20, Sung in Figs. 1A, 5 and Annotated Fig. 1A teaches a semiconductor device 1000 (Fig. 5, ¶ 12 & ¶ 57-¶ 58, computing system 1000 including DRAMs comprising DRAM cells; Fig. 1A & ¶ 21, memory cell 100 i.e., DRAM cell), comprising single-gate vertical transistors 180 (Figs. 1A, 5, ¶ 12, ¶ 21, ¶ 57-¶ 58, transistors 180, as there are multiple memory cells 100 in the device 1000) and storage units 180 (Figs. 1A, 5, ¶ 12, ¶ 21, ¶ 57-¶ 58, capacitors 150, as there are multiple memory cells 100 in the device 1000) coupled with the single-gate vertical transistors 180 correspondingly, wherein
two adjacent single-gate vertical transistors 180 in a lateral direction are separated by an isolation structure 110 (Fig. 1A, ¶ 21, third isolation material 110 would separate laterally adjacent transistors 180) and share a U-shaped semiconductor layer 182 (Fig. 1A, ¶ 25, semiconductor material 182) covering both sides of the isolation structure 110 in the lateral direction (Figs. 1A, 5, Annotated Fig. 1A, the memory cells 100 of the device 1000 must be placed laterally, and the semiconductor layer 180 would cover sides of the isolation structure 110); and
a gate structure 104 (Fig. 1A, ¶ 27, conductor 104 having a gate length i.e., gate conductor) of the single-gate vertical transistor 180 is coupled with a side (Fig. 1A, right side; Annotated Fig. 1A, gate structure 104 and the portion 182V are connected to each other through the layer 184) of the semiconductor layer 182 opposite to the isolation structure 110 (Fig. 1A, the gate structure 104 is coupled to the right side of the semiconductor layer 182, which is opposite to the isolation structure 110 on the left side of the semiconductor layer 182).
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claims 6-8 are objected to as being dependent upon a rejected base claim, but would be allowable if (i) rewritten in independent form to include all of the limitations of the base claim and any intervening claims or (ii) the objected claim and any intervening claims are fully incorporated into the base claim.
Claim 6 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 6, wherein the isolation structure comprises: a conductor layer; and a dielectric layer surrounding the conductor layer.
Claim 7 would be allowable, because claim 7 depends from the allowable claim 6.
Claim 8 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 8, bit lines extending in the lateral direction and directly coupled with the vertical transistors through the first lateral portions of the semiconductor layers of the vertical transistors.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2022/0068932 A1 to Hwang et al. relates to an integrated assembly having first conductive structures extending along a first direction. Spaced-apart upwardly-opening container-shapes are over the first conductive structures, in which each of the container-shapes has a first sidewall region, a second sidewall region, and a bottom region extending from the first sidewall region to the second sidewall region. Each of the first and second sidewall regions includes a lower source/drain region, an upper source/drain region, and a channel region between the upper and lower source/drain regions. The lower source/drain regions are electrically coupled with the first conductive structures. Second conductive structures extend along a second direction which crosses the first direction. The second conductive structures have gate regions operatively adjacent the channel regions. Storage elements are electrically coupled with the upper source/drain regions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIKKA LIU whose telephone number is (571)272-2568. The examiner can normally be reached on 9AM-5AM EST M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.L./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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