DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8,11-15,19-21 and 24-27 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2006/0130303 A1 (Yamasaki).
Yamasaki discloses, referring primarily to figures 1 and 3A-G, a printed circuit board, comprising: an interconnect bridge (200, 204) including an insulating material (204), a plurality of conductive pattern layers (201, 202, 203) respectively disposed on or in the insulating material, and a conductive post (200) disposed on the insulating material; a first insulating layer (401, 501) embedding the interconnect bridge and having a recess portion exposing a portion of the conductive post (figure 3E); and a first wiring layer (503, near h1 as shown in figure 3F) disposed on the first insulating layer and including a first pad pattern connected to the exposed portion of the conductive post on the recess portion (figure 3F) [claim 1], wherein the first wiring layer further comprises a second pad pattern (503, on the far left as shown in figure 3F) disposed in a region other than the recess portion and spaced apart from the conductive post, and an upper surface of the first pad pattern and an upper surface of the second pad pattern have a step portion from each other [claim 2], wherein one portion of the conductive post is embedded in the first insulating layer and another portion (near H5 as shown in figure 3F) thereof protrudes from an upper surface of the first insulating layer [claim 3], wherein the first pad pattern is disposed on the upper surface of the first insulating layer on the recess portion to cover the another protruding portion of the conductive post (figure 3F) [claim 4], wherein the first pad pattern comprises: a first metal layer covering the upper surface of the first insulating layer and an upper surface and a side surface of the another protruding portion of the conductive post with a substantially constant thickness; and a second metal layer disposed on the first metal layer and having an average thickness thicker than the first metal layer (502B) [claim 5], wherein the conductive post is embedded in the first insulation layer and is exposed from an upper surface of the first insulating layer so that an upper surface of the conductive post is substantially coplanar with the upper surface of the first insulating layer (figure 3F) [claim 6], wherein the first pad pattern (503) is disposed on the upper surface of the first insulating layer on the recess portion to cover the exposed upper surface of the conductive post [claim 7], wherein the first pad pattern comprises: a first metal layer covering the upper surface of the first insulating layer and the exposed upper surface of the conductive post with a substantially constant thickness, and a second metal layer disposed on the first metal layer and having an average thickness thicker than the first metal layer [claim 8], wherein a conductive pattern layer disposed on an uppermost side, among the plurality of conductive pattern layers, is disposed on an upper surface of the insulating material, and the conductive pattern layer disposed on the uppermost side comprises a conductive pad connected to the conductive post and a first ground pattern spaced apart from the conductive post ([0039]) [claim 11], wherein a conductive pattern layer disposed on a lowermost side, among the plurality of conductive pattern layers, is in contact with an adhesive (401) attached to a lower side of the interconnect bridge, and the conductive pattern layer disposed on the lowermost side comprises a second ground pattern ([0039]) [claim 12], further comprising: a second wiring layer (303) disposed in the first insulating layer; a first via layer (502) penetrating through the first insulating layer and connecting the first and second wiring layers; a second insulating layer (301, 305) disposed below the first insulating layer; a third wiring layer (304) disposed in the second insulating layer; a second via layer (302) penetrating through the second insulating layer and connecting the second and third wiring layers; a third insulating layer (601) disposed on the first insulating layer and covering the first wiring layer; a fourth wiring layer (603) disposed on the third insulating layer; and a third via layer (602) penetrating through the third insulating layer and connecting the first and fourth wiring layers, wherein an upper surface of the third insulating layer above is substantially flat [claim 13], wherein the recess portion is tapered so that a width (H5) of an upper end thereof is larger than a width (H1) of a lower end thereof on a cross-section [claim 14], wherein the conductive post has an aspect ratio of more than 1 ([0070]) [claim 15].
Similarly, Yamasaki discloses, a printed circuit board, comprising: an interconnect bridge (200, 204) including an insulating material (204), a plurality of conductive pattern layers (201, 202, 203) respectively disposed on or in the insulating material, and a conductive post (200) disposed on an upper surface of the insulating material; a first insulating layer (401, 501) embedding the interconnect bridge and being in contact with at least a portion of the upper surface of the insulating material; a first wiring layer (503) disposed on the first insulating layer and including a first pad pattern to be in contact with the conductive post; a second wiring layer (303) disposed in the first insulating layer; and a first via layer (502) penetrating through the first insulating layer and connecting the first and second wiring layers [claim 19], wherein one portion of the conductive post is embedded in the first insulating layer and another portion thereof protrudes from an upper surface of the first insulating layer (figure 3F) [claim 20], wherein the conductive post is embedded in the first insulation layer and is exposed from an upper surface of the first insulating layer so that an upper surface of the conductive post is substantially coplanar with the upper surface of the first insulating layer (figure 3F) [claim 21], wherein a conductive pattern layer (503) disposed on an uppermost side, among the plurality of conductive pattern layers, is disposed on an upper surface of the insulating material, and the conductive pattern layer disposed on the uppermost side comprises a conductive pad connected to the conductive post [claim 24], wherein the conductive pattern layer further comprises a first ground pattern spaced apart from the conductive post ([0039]) [claim 25], wherein a conductive pattern layer disposed on a lowermost side, among the plurality of conductive pattern layers, is in contact with an adhesive (401) attached to a lower side of the interconnect bridge, and the conductive pattern layer disposed on the lowermost side comprises a second ground pattern ([0039]) [claim 26], further comprising: a second insulating layer (301, 305) disposed below the first insulating layer; a third wiring layer (304) disposed in the second insulating layer; a second via layer (302) penetrating through the second insulating layer and connecting the second and third wiring layers; a third insulating layer (601) disposed on the first insulating layer and covering the first wiring layer; a fourth wiring layer (603) disposed on the third insulating layer; and a third via layer (602) penetrating through the third insulating layer and connecting the first and fourth wiring layers [claim 27].
Allowable Subject Matter
Claims 16-18 are allowed.
Claims 9, 10, 22 and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claims 9 and 10 state the limitation “the interconnect bridge further comprises a protective material disposed on the insulating material and covering at least one of the plurality of conductive posts, and the protective material is disposed in a partial region on an upper surface of the insulating material.” This limitation, in conjunction with the other claimed features, was neither found to be disclosed in, nor suggested by the prior art.
Claims 16-18 state the limitation “at least one of the plurality of second wiring layers has a smaller average pitch than at least one of the plurality of first wiring layers, and at least one of the plurality of first insulating layers has a step region exposing a portion of each of the plurality of conductive posts.” This limitation, in conjunction with the other claimed features, was neither found to be disclosed in, nor suggested by the prior art.
Claims 22 and 23 state the limitation “wherein the conductive post is provided in plural form, the interconnect bridge further comprises a protective material disposed on the insulating material and covering at least one of the plurality of conductive posts, and the protective material is disposed in a partial region on the upper surface of the insulating material." This limitation, in conjunction with the other claimed features, was neither found to be disclosed in, nor suggested by the prior art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEREMY C NORRIS whose telephone number is (571)272-1932. The examiner can normally be reached 7:15-15:15 M-F.
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JEREMY C. NORRIS
Examiner
Art Unit 2847
/JEREMY C NORRIS/Primary Examiner, Art Unit 2847