CTNF 18/666,120 CTNF 84714 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 14 and 16 is/are rejected under 35 U.S.C. 102 (a)(1)/(a)(2) as being anticipated by Lin (US 2022/0359208) . Regarding claim 14 , Lin discloses a semiconductor device, comprising: a substrate (Fig.3, numeral 218); an active pattern (224), (212) extending on the substrate (218) in a first direction; a plurality of channel layers (224) arranged on the active pattern (212) and spaced apart from each other in a direction perpendicular to an upper surface of the substrate (218); a gate structure (310) crossing the active pattern, and surrounding the plurality of channel layers (224), and the gate structure (310) extending in a second direction intersecting the first direction; fence spacers (226) on both side surfaces of the active pattern in the second direction at both sides of the gate structure (310); source/drain patterns (202) including epitaxial layers connected to side surfaces of the plurality of channel layers (224), respectively, on a portion of the active pattern on both sides of the gate structure, and the source/drain patterns having a trench in the epitaxial layer (202); and contact structures (310) on the source/drain patterns (202), respectively, each contact structure including a first extension portion filling the trench, and a pair of second extension portions (310) extending to the fence spacers (226), respectively, along both side surfaces of each of the source/drain patterns (202) in the second direction. Regarding claim 16 , Lin discloses a metal-semiconductor compound layer (322) between the source/drain patterns (202) and the contact structures (310) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2022/0359208) in view of Chang (US 2024/0055485) . Regarding claim 1 , Lin discloses a semiconductor device, comprising: a substrate (Fig. 3, numeral 218); an active pattern extending on the substrate in a first direction (Fig.2); a device isolation layer (230) on the substrate (218) and defining the active pattern; a plurality of channel layers (Fig.3, numeral 220) arranged on the active pattern and spaced apart from each other in a direction perpendicular to an upper surface of the substrate (218); a gate structure (348) crossing the active pattern ([0027]), and surrounding the plurality of channel layers (220), and the gate structure extending in a second direction intersecting the first direction (Fig.2); source/drain patterns (202) including a first epitaxial layer (306) on a portion of the active pattern at both sides of the gate structure along side surfaces of the plurality of channel layers ([0028]) and having a trench (Fig.3); contact structures (310) on the source/drain patterns (202), respectively, and including a first extension portion filling the trench (Fg.3, part of (310) in the trench), and a pair of second extension portions (part of (310) above the trench) extending along both side surfaces of each of the source/drain patterns (2020 in the second direction, respectively; and a metal-semiconductor compound layer (322) between the source/drain patterns (202) and the contact structures (310). Lin does not disclose a second epitaxial layer on the first epitaxial layer. Chang however discloses a second epitaxial layer (Fig.13, numeral 146c) on the first epitaxial layer (146a); (146b) ([0035]). It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Lin with Chang to have a second epitaxial layer on the first epitaxial layer for the purpose of forming source/drain regions (Chang, [0025]). Regarding claim 2 , Lin discloses wherein the first extension portion (310) of the contact structures has at least a portion overlapping a lowest channel layer (224) of the plurality of channel layers in a direction parallel to the upper surface of the substrate (218) (Fig.3). Regarding claim 3, Lin discloses wherein a portion of the contact structures (Fig.3, upper part of (310)) adjacent to the gate structure (348) has a width in the second direction greater than a width in the second direction of the first extension portion (Fig.3). Regarding claim 4, Lin in view of Chang discloses wherein the second extension portions (310) of the contact structures extend along a surface of the second epitaxial layer of the source/drain patterns (upper part of (202)). Regarding claim 5, Lin discloses wherein the second extension portions (upper part of (310)) of the contact structures extend up to the device isolation layer (230) (Fig.2). Regarding claim 6 , Lin discloses fence spacers (226) on both side surfaces of the active pattern (212) in the second direction (Fig.3). Regarding claim 7 , Lin discloses wherein the second extension portions (upper part of (310) of the contact structures extend to the fence spacers (226). Regarding claim 8 , Lin does not disclose wherein a difference between a maximum width of the source/drain patterns in the second direction and a width of a portion of the source/drain patterns between the fence spacers is 20 nm or less. Lin however discloses that channel length is controlled between adjacent metal fills ([0025]). It would have been thereof obvious to one of ordinary skill in the art at the time the invention was filed to have a difference between a maximum width of the source/drain patterns in the second direction and a width of a portion of the source/drain patterns between the fence spacers to be in the claimed range for the purpose of controlling the channel length of the device (Lin, [0025]). Regarding claim 9, Lin discloses wherein a portion of the source/drain patterns (202), arranged above the fence spacers (226), does not have a convex portion on both side surfaces in the second direction (Fig.3). Regarding claim 10 , Lin discloses wherein the source/drain patterns (202) is P-type source/drain patterns ([0021]). Regarding claim 11 , Chang discloses wherein each of the first epitaxial layer and the second epitaxial layer includes silicon germanium (SiGe), and a first concentration of germanium (Ge) in the first epitaxial layer (146a); (146b) is lower than a second concentration of germanium (Ge) in the second epitaxial layer (146c) ([0036]; [0037]; [0038]). Regarding claim 12 , Chang discloses wherein a second concentration of the second epitaxial layer (146c) is 30 atomic% to 70 atomic% ([0038]) Chang does not disclose that a first concentration of the first epitaxial layer is 5 atomic% to 20 atomic%. Chang however discloses that the first epitaxial layer serves as a as lattice transitional layer ([0037]). It would have been therefore obvious to one of ordinary skill in the art at the time the invention was field to adjust the germanium concentration in the first epitaxial layer to be in the claimed range for the purpose of optimization transitional properties of the first epitaxial layer. Regarding claim 13 , Chang discloses internal spacers (178) on both side surfaces of the gate structure (182) in the first direction below a lower surface of each of the plurality of channel layers (106) . 07-21-aia AIA Claim (s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin . Regarding claim 15 , Lin does not disclose wherein a maximum width of the source/drain patterns in the second direction is less than 120% of a width of a portion of the source/drain patterns between the fence spacers. Lin however discloses that channel length is controlled between adjacent metal fills ([0025]). It would have been thereof obvious to one of ordinary skill in the art at the time the invention was filed to have a maximum width of the source/drain patterns in the second direction is less than 120% of a width of a portion of the source/drain patterns between the fence spacers to be in the claimed range for the purpose of controlling the channel length of the device (Lin, [0025]) . 07-22-aia AIA Claim (s) 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to claim 14 above, and further in view of Chang . Regarding claim 17 , Lin discloses does not disclose wherein an epitaxial layer of the source/drain patterns includes: a first epitaxial layer on a portion of the active pattern alongside surfaces of the plurality of channel layers, and a second epitaxial layer on the first epitaxial layer and defining the trench. Chang however discloses wherein an epitaxial layer of the source/drain patterns includes: a first epitaxial layer (Fig.17, numeral 146, 146b) on a portion of the active pattern along side surfaces of the plurality of channel layers (106), and a second epitaxial layer (146c) on the first epitaxial layer and defining the trench (Fig. 17). It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Lin with Chang to have a first epitaxial layer on a portion of the active pattern along side surfaces of the plurality of channel layers, and a second epitaxial layer on the first epitaxial layer and defining the trench for the purpose of forming source/drain regions (Chang, [0025]). Regarding claim 18, Lin in view of Chang discloses wherein the second extension portions of the contact structures (upper part of (310) extend along side surfaces of the second epitaxial layer (upper part of (202)) (Fig.3). Regarding claim 19 , Lin discloses a semiconductor device, comprising: a substrate (Fig.3, numeral 218); an active pattern (224), (212) extending on the substrate (218) in a first direction; a plurality of channel layers (224)arranged on the active pattern and spaced apart from each other in a direction perpendicular to an upper surface of the substrate (218); a gate structure (348) crossing the active pattern, surrounding the plurality of channel layers (224) , and extending in a second direction intersecting the first direction; source/drain patterns (2020 including, and a second epitaxial layer (202) having a trench deeper than a level of an upper surface of a lowermost channel layer (224) among the plurality of channel layers; contact structures (310) on the source/drain patterns (202), respectively, each contact structure (310) including a first extension portion filling the trench and a pair of second extension portions (upper part of (310)) extending along both side surfaces of each of the source/drain patterns (202) in the second direction; and a metal-semiconductor compound layer (322) between the source/drain patterns (202) and the contact structures (310). Lin does not disclose a first epitaxial layer along side surfaces of the plurality of channel layers on a portion of the active pattern and that the second epitaxial layer is on the first epitaxial layer. Chang however discloses a first epitaxial layer (Fig.17, numerals 146b) along side surfaces of the plurality of channel layers (106) on a portion of the active pattern and that the second epitaxial layer (146c) is on the first epitaxial layer (146b). It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Lin with Chang to have a first epitaxial layer along side surfaces of the plurality of channel layers on a portion of the active pattern and that the second epitaxial layer is on the first epitaxial layer for the purpose of forming source/drain regions (Chang, [0025]). Regarding claim 20 , Chang discloses wherein each of epitaxial layers (146b), (146c) of the source/drain patterns includes an epitaxial layer doped with P-type impurities ([0037]; [0038]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JULIA SLUTSKER whose telephone number is (571)270-3849. The examiner can normally be reached Monday-Friday, 9 am-6 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JULIA SLUTSKER/ Primary Examiner, Art Unit 2891 Application/Control Number: 18/666,120 Page 2 Art Unit: 2891 Application/Control Number: 18/666,120 Page 3 Art Unit: 2891 Application/Control Number: 18/666,120 Page 4 Art Unit: 2891 Application/Control Number: 18/666,120 Page 5 Art Unit: 2891 Application/Control Number: 18/666,120 Page 6 Art Unit: 2891 Application/Control Number: 18/666,120 Page 7 Art Unit: 2891 Application/Control Number: 18/666,120 Page 8 Art Unit: 2891 Application/Control Number: 18/666,120 Page 9 Art Unit: 2891 Application/Control Number: 18/666,120 Page 10 Art Unit: 2891
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