DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated09/08/2026.
Claims 1-44 are pending in this application.
Applicant made a provisional election to prosecute the invention of Group I, Species I and III, claims 1-15, 18-21, 25-34, 42, and 44, is acknowledged.
Claims 16-17, 22-24, 35-41, and 43 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-elected group there being no allowable generic or linking claim.
Applicant has the right to file a divisional application covering the subject matter of the non-elected claims.
Acknowledges
2. Receipt is acknowledged of the following items from the Applicant.
Information Disclosure Statement (IDS) filed on 05/16/2024. The references cited on the PTOL 1449 form have been considered.
Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609.
Foreign Priority
3. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been placed of record in the file.
Specification
4. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1-10, 14, 18-21, 25-34, 42, and 44 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (US 2020/0075496)
Regarding claim 1, Yu discloses a printed circuit board comprising:
a first insulating layer 138 (see Figs. 1, Fig. 3, Fig. 7: the first insulating layer 138 in Fig. 1 or Fig. 3 is equivalent to the lower insulating layer in second RDL 160 adjacent to underfill layer 750 in fig. 7; that is, Figs. 1, 3 can be turned upside-down);
a first metal layer 152 (Fig. 1J) having a first portion 155 protruding upwardly of the first insulating layer 138 and a second portion 156 embedded in the first insulating layer 138; and
a barrier layer 148 and/or 150 (Fig. 1J; paras. 0028, 0030, 0041) disposed between the first insulating layer 138 and the second portion 156 and extending to a lower surface (surface which in contact with layer 162 in Fig. 1K) of the first insulating layer 138, wherein the first portion 155 and the second portion 156 are integrated.
Regarding claim 2, Yu discloses the printed circuit board of claim 1, wherein a width of a lower surface of the first portion 155 is narrower than a width of an upper surface of the second portion 156. See Fig. 1J, Fig. 7.
Regarding claim 3, Yu discloses the printed circuit board of claim 1, wherein the first portion 155 and the second portion 156 respectively have a tapered shape, and a tapered direction of the first portion and a tapered direction of the second portion are substantially the same. See Fig. 1J, Fig. 7.
Regarding claim 4, Yu discloses the printed circuit board of claim 3, wherein the second portion 156 has the tapered shape having a width becoming narrower toward a top. See Figs. 1J, Fig. 7.
Regarding claim 5, Yu discloses the printed circuit board of claim 1, wherein at least a portion of an upper surface of the second portion 156 is not covered by the first insulating layer 138. See Fig. 1J, Fig. 7.
Regarding claim 6, Yu discloses the printed circuit board of claim 1, wherein the first metal layer 152 includes a first recess, such that an upper surface of the second portion 156 and an upper surface of the first insulating layer 138 have a step. See Fig. 1J, Fig. 7: The recess is filled by part of the barrier layer 148/150; the upper surface of the second portion 156 is lower that that of the upper surface of the first insulating layer 138, forming the recess.
Regarding claim 7, Yu discloses the printed circuit board of claim 6, wherein a depth of the first recess is substantially equal to a thickness of the barrier layer 148 & 150. See Fig. 1J, Fig. 7.
Regarding claim 8, Yu discloses the printed circuit board of claim 1, wherein the first metal layer 152 includes a seed layer 150 and a plating layer 155 & 156 disposed on the seed layer 150, wherein the seed layer 150 is disposed outside the first metal layer (the seed layer 150 exposes to second trace 126’ and/or to passivation layer 162, Fig. 1K).
Regarding claim 9, Yu discloses the printed circuit board of claim 8, wherein the seed layer 150 is provided integrally along an outer side of the first portion 155 and an outer side of the second portion 156. See Fig. 1J.
Regarding claim 10, Yu discloses the printed circuit board of claim 9, wherein the plating layer 155 & 156 is integrally provided with the first portion 155 and the second portion 156. See Fig. 1J, and para. 0031.
Regarding claim 14, Yu discloses the printed circuit board of claim 1, wherein a lower surface of the first metal layer 152 and a lower surface of the barrier layer 148/150 are substantially coplanar. See Fig. 7.
Regarding claim 18, Yu discloses the printed circuit board of claim 1, further comprising a solder resist layer 136 (Fig. 1J, Fig. 7) disposed on the first insulating layer 138, wherein the first metal layer 155 penetrates through the solder resist layer 136 and at least a portion of the first portion 155 protrudes from the solder resist layer 136 (protruding into the first insulting layer 138 and connected/integrated with the second portion 156).
Regarding claim 19, Yu discloses the printed circuit board of claim 18, wherein the barrier layer 148/150 extends between the first metal layer 152 and the solder resist layer 136. See Fig. 1J, Fig. 7.
Regarding claim 20, Yu discloses the printed circuit board of claim 1, further comprising:
a first connecting member 122 (Fig. 3) disposed on the first metal layer 152; and
a first electronic component 302a/b, 702a/b disposed on the first connecting member 122 and connected to the first metal layer 152. See Fig. 3, Fig. 7.
Regarding claim 21, Yu discloses the printed circuit board of claim 1, wherein the first metal layer 152 includes a first metal post 155 and a second metal post 156, wherein a thickness of the first metal post is greater than a thickness of the second metal post.
Para. 0027: the angles θ1 and θ2 forming the trench openings in which the metal layers are located ranges from 80 degrees to 90 degrees. Accordingly, when the angles are 90 degrees, the metal layers would form metal posts. The thickness of the first metal post 155 would be greater than that of the second metal post 156 since the first metal post 155 extends into the first insulating layer 138, wherein the thicknesses of insulating layers 136 and 138 are substantially equal, both ranging from 0.5 μm to 5 μm (see paras. 0020, 0022). Furthermore, the insulating layers 136 and 138 inherently should be formed similarly to insulating layers 106, 108, respectively.
Regarding claim 25, Yu discloses the printed circuit board of claim 1, wherein the barrier layer 148/150 extends to cover at least a portion of the first portion 155. See Fig. 1J.
Regarding claim 26, Yu discloses the printed circuit board of claim 25, wherein the barrier layer 148/150 covers an upper surface of the second portion 156. See Fig. 1J, Fig. 7.
Regarding claim 27, Yu discloses the printed circuit board of claim 26, wherein the barrier layer 148/150 covers substantially an entirety of the second portion 156. See Fig. 1J, Fig. 7.
Regarding claim 28, Yu discloses the printed circuit board of claim 25, further comprising a first connecting member 122, or alternately, a first connecting member 168 (Fig. 3) disposed on a portion of the first portion 155 (according to the instant claim language, the first connecting member may not necessarily be in contact with the first portion), wherein the barrier layer 148/168 is not disposed on a portion of the first portion 155 in (electrical) contact with the first connecting member 122. See Fig. 1J, Fig. 1K, Fig. 3.
Regarding claim 29, Yu discloses the printed circuit board of claim 28, wherein the first connecting member 122/168 covers at least a portion of an upper surface and at least a portion of a side surface of the first portion 155 (view from the side of die 302a). See Fig. 1K, Fig. 3.
Regarding claim 30, Yu discloses the printed circuit board of claim 28, wherein the first connecting member 168 includes a first metal, and the barrier layer includes an oxide of the first metal. See para. 0039.
Regarding claim 31, Yu discloses the printed circuit board of claim 30, wherein the first metal includes aluminum (Al). See para. 0047.
Regarding claim 32, Yu discloses the printed circuit board of claim 1, wherein the barrier layer 148 does not cover an upper surface of the first insulating layer 138. See Fig. 7.
Regarding claim 33, Yu discloses the printed circuit board of claim 1, wherein the barrier layer 148/150 includes at least one material selected from Al2O3, SiO2, TiO2, ZnO, ZrO2, HfO2, or La2O3. See paras. 0028, 0039, 0041, 0047.
Regarding claim 34, Yu discloses the printed circuit board of claim 1:
(Claim 1: a printed circuit board comprising:
a first insulating layer 108 (see Figs. 1, Fig. 3, Fig. 7);
a first metal layer 122 (Fig. 1I, Fig. 1J) having a first portion 125 or 125’ protruding upwardly of the first insulating layer 108 (into dielectric layer 106) and a second portion 126/126’ embedded in the first insulating layer 108; and
a barrier layer 118 and/or 120 (Fig. 1I) disposed between the first insulating layer 108 and the second portion 126/126’ and extending to a lower surface of the first insulating layer 108, wherein the first portion 125’/125 and the second portion 126’/126 are integrated (note that the structure in Fig. 1K can be turned upside-down such that the first insulating layer 108 in Fig. 1K would be equivalent to the lower dielectric layer in the first RDL 130 in Fig. 7, such lower dielectric layer is adjacent to the second RDL 160))
further comprising:
a second insulating layer 136 (see Fig. 3, Fig. 7) disposed below the first insulating layer 108;
a first wiring layer 156 disposed on the second insulating layer 136; and
a first via layer 155 penetrating through at least a portion of the second insulating layer 136 to connect the first wiring layer 156 and the first metal layer 122.
Regarding claim 42, Yu discloses the printed circuit board of claim 34, wherein the barrier layer 118/120 is spaced apart from the first via layer 155. See Fig. 1J, Fig. 1K, Fig. 3.
Regarding claim 44, Yu discloses the printed circuit board of claim 1, wherein side surfaces of the first portion and the second portion have a step therebetween. See Figs. 1, Fig. 3, Fig. 7.
7. Claims 1, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sundaram et al. (US 2016/0111380)
Regarding claim 1, Sundaram discloses a printed circuit board comprising:
a first insulating layer 218 (glass core, see Fig. 2, Fig. 10);
a first metal layer 212 having a first portion protruding upwardly (over top surface of barrier layer 214) of the first insulating layer 218 and a second portion embedded in the first insulating layer 218; and
a barrier layer 214 disposed between the first insulating layer 218 and the second portion and extending to a lower surface of the first insulating layer 218, wherein the first portion and the second portion are integrated.
Regarding claim 15, Sundaram discloses the printed circuit board of claim 14, wherein the lower surface of the first metal layer 212 protrudes further than an extended surface of the lower surface of the first insulating layer 218.
Claim Rejections - 35 U.S.C. § 103
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2020/0075496) in view of Koduri (US 2019/0109105)
Regarding claim 11, Yu discloses the printed circuit board of claim 1, comprising all claimed limitation, as discussed above, except for further comprising a surface treatment layer disposed on the first metal layer.
Koduri discloses a printed circuit board comprising a first metal layer 114, a barrier layer 112, and a surface treatment layer 118 disposed on the first metal layer 114.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Yu to further include a surface treatment layer, as that taught by Koduri, in order to lower the resistance, to improve reliability, to provide robust solder joint, and/or to protect the metal layer. See para. 0038 of Koduri.
Regarding claim 12, Yu/Koduri discloses the printed circuit board of claim 11, wherein a thickness of the surface treatment layer 118 is greater than a thickness of the barrier layer 112. See paras. 0037, 0038 of Koduri.
Allowable Subject Matter
10. Claim 13 is allowable.
Claim13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed printed circuit board (in addition to the other limitations in the claim) wherein the first metal layer includes a first recess such that an upper surface of the second portion and an upper surface of the first insulating layer have a step, and the surface treatment layer is disposed at least in the first recess.
Conclusion
11. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 October 10, 2026
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