DETAILED ACTION
Election/Restrictions
Applicant's election with traverse of Group I (claims 1-10 and 12-15) in the reply filed on August 10, 2026 is acknowledged. The traversal is on the grounds stated by the applicant in the paper filed on August 10, 2026, on pages 2-3.
This is not found persuasive because the MPEP states restriction is proper when a device can be made by a materially different process or vice versa (MPEP citation). Claim 11 is directed at a semiconductor package formed by the method of Claim 1. Limitations such as curing conductive and non-conductive materials are product-by-process and do not bear weight (See MPEP 2113). A semiconductor package may be made by applying conductive and non-conductive material that do not require curing, which would be a device made by a materially different process. The relevance of arguments to GATT are not readily apparent. Therefore, the requirement for restriction stands.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 6-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Leal et al. (US 2010/0140811 A1, hereinafter referred to as ‘Leal’).
As to claim 1, Leal teaches a method (see e.g. figures 11A-D) of manufacturing a semiconductor device package comprising a die, a substrate, a first connection area and a second connection area,
wherein the first connection area provides an electrical connection to the die,
wherein the second connection area provides an electrical connection to one of a substrate bond pad, a leadframe and a clip frame provided on the substrate,
wherein the first connection area and the second connection area are facing in the same direction,
wherein the method comprises the steps of:
applying a non-conductive material (e.g. 1966) between an edge of the first connection area and an edge of the second connection area and along a side of the die (e.g. 1151), and curing the non-conductive material, thereby forming a first body of non-conductive material; and
applying one or more of a conductive material (1961) between the first connection area and the second connection area and along a surface of the first body of non-conductive material, and curing the conductive material, thereby forming a second body of conductive material.
See also paragraphs 0088-0097 and annotated figure 11D below.
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As to claim 6, “wherein the method does not perform an etching or material removing of superfluous material from the first body of non-conductive material” - Leal does not teach an etching or material removing of superfluous material from the first body of non-conductive material.
As to claim 7, Leal teaches the first connection area is an area on the die (1151). See annotated figure 11D above.
As to claim 8, Leal teaches the die is provided face down on the substrate; a face of the die is facing downward toward the substrate, as shown in figure 11D.
As to claim 9, Leal teaches the first connection area is an area on a bond pad provided on the die. See annotated figure 11D above.
As to claim 10, Leal teaches the die is provided face up on the substrate; a face of the die is facing upward on the substrate, as shown in figure 11D.
Claims 1 and 6-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hashimoto (US 7,514,350 B2).
As to claim 1, Hashimoto teaches a method (see e.g. figures 3A-3C) of manufacturing a semiconductor device package comprising a die (10), a substrate (20), a first connection area and a second connection area (see annotated figure 3A below),
wherein the first connection area provides an electrical connection to the die,
wherein the second connection area provides an electrical connection to one of a substrate bond pad, a leadframe and a clip frame provided on the substrate,
wherein the first connection area and the second connection area are facing in the same direction,
wherein the method comprises the steps of:
applying a non-conductive material (30) between an edge of the first connection area and an edge of the second connection area and along a side of the die, and curing the non-conductive material, thereby forming a first body of non-conductive material; and
applying one or more of a conductive material (34) between the first connection area and the second connection area and along a surface of the first body of non-conductive material, and curing the conductive material (col. 7, lines 21 et seq), thereby forming a second body of conductive material.
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As to claim 6, “wherein the method does not perform an etching or material removing of superfluous material from the first body of non-conductive material” - Hashimoto does not teach an etching or material removing of superfluous material from the first body of non-conductive material.
As to claim 7, Hashimoto teaches the first connection area is an area on the die. See annotated figure 3A above.
As to claim 8, Hashimoto teaches the die is provided face down on the substrate; a face of the die is facing downward toward the substrate, as shown in figure 3A.
As to claim 9, Hashimoto teaches the first connection area is an area on a bond pad (14) provided on the die. See figure 3A.
As to claim 10, Hashimoto teaches the die is provided face up on the substrate; a face of the die is facing upward on the substrate, as shown in figure 3A.
Claims 1, 4, and 6-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hamilton et al. (US 11,233,030 B1, hereinafter referred to as ‘Hamilton’).
As to claim 1, Hamilton teaches a method (see e.g. figure 1A) of manufacturing a semiconductor device package comprising a die (104), a substrate (106), a first connection area and a second connection area (see annotated figure 1A below),
wherein the first connection area provides an electrical connection to the die,
wherein the second connection area provides an electrical connection to one of a substrate bond pad, a leadframe and a clip frame provided on the substrate,
wherein the first connection area and the second connection area are facing in the same direction,
wherein the method comprises the steps of:
applying a non-conductive material (116) between an edge of the first connection area and an edge of the second connection area and along a side of the die, and curing the non-conductive material, thereby forming a first body of non-conductive material; and
applying one or more of a conductive material (102) between the first connection area and the second connection area and along a surface of the first body of non-conductive material, and curing the conductive material (col. 4, lines 49 et seq), thereby forming a second body of conductive material.
As to claim 4, Hamilton teaches the step curing of the conductive material is sintering (col. 4, lines 49 et seq).
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As to claim 6, “wherein the method does not perform an etching or material removing of superfluous material from the first body of non-conductive material” - Hamilton does not teach an etching or material removing of superfluous material from the first body of non-conductive material.
As to claim 7, Hamilton teaches the first connection area is an area on the die. See annotated figure 1A above.
As to claim 8, Hamilton teaches the die is provided face down on the substrate; a face of the die is facing downward toward the substrate, as shown in figure 1A.
As to claim 9, Hamilton teaches the first connection area is an area on a bond pad (110) provided on the die. See figure 1A.
As to claim 10, Hamilton teaches the die is provided face up on the substrate; a face of the die is facing upward on the substrate, as shown in figure 3A.
Allowable Subject Matter
Claims 2, 3, and 5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. (Claims 12-15 are also objected to as being dependent upon an objected claim.)
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: see the attached form PTO-892 for pertinent cited art.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Scott B. Geyer (telephone: 571-272-1958). The examiner can normally be reached on Monday to Friday, 10AM - 4PM (ET). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at: http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim (telephone: 571-272-8458). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only.
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/SCOTT B GEYER/ Primary Examiner, Art Unit 2812
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