Prosecution Insights
Last updated: April 19, 2026
Application No. 18/666,312

OPTICAL MODULE AND OPTICAL TRANSCEIVER

Non-Final OA §103
Filed
May 16, 2024
Examiner
TRAN, BINH BACH THANH
Art Unit
2848
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Fujitsu Optical Components Limited
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
92%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allow Rate
545 granted / 680 resolved
+12.1% vs TC avg
Moderate +12% lift
Without
With
+12.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
28 currently pending
Career history
708
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
54.1%
+14.1% vs TC avg
§102
35.3%
-4.7% vs TC avg
§112
8.5%
-31.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 680 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1 - 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sugiyama (US 20160356955), in view of Muto (US 20070102830). Regarding claim 1, An optical module, comprising: a first component (the optical modulator 120, Fig. 2); a second component (the driver 140); and a flexible substrate (an FPC 130) that electrically connects the first component (120) and the second component (140), wherein the flexible substrate includes a signal pad (signal pad 321, 331, Fig. 3) at least a part of which is fixed to the first component (the pads on the optical modulator side 120 is fixed on the optical modulator 120, Fig. 2, as the FPC 130 is fixed on to the optical modulator 120), a ground pad (322, 332; Fig. 3) at least a part of which is fixed to the first component (the pads on the optical modulator side 120 is fixed on the optical modulator 120, Fig. 2, as the FPC 130 is fixed on to the optical modulator 120), a signal line (the microstrip line 333) that is formed on a first surface (bottom surface of the FPC 130) of the flexible substrate and connects the signal pad (331, 321) and the second component (140), the signal line having a width narrower than the signal pad (tapered segment 331a), a ground pattern (a grounding pattern 323) that is formed on a second surface (top surface of the FPC 130) serving as a rear surface of the first surface, a first coverlay (the coverlay 205) including a first protrusion part (a protrusion 205a) that is formed on the first surface, covers a region on the flexible substrate where the signal line (333) is disposed, and protrudes at a location where the signal pad (331, 331a) is disposed, toward an end part of the flexible substrate on the first component side than the region where the signal line is disposed (the signal line is on the side of the component 120). Sugiyama does not explicitly disclose a second coverlay including a second protrusion part that is formed on the second surface, protrudes at a location where the signal pad is disposed, toward an end part of the flexible substrate on the first component side, and covers a region on the ground pattern facing at least the signal pad. Muto suggests a coverlay layers (102, 106, 108) on both sides of the circuit board (100, Fig.8). Sugiyama suggests a protrusion (205a) on the overlay layer 205. It would have been obvious to one having skill in the art at the effective filing date of the invention to cover both surface of the circuit board and modify the shape of the coverlay layer in order to provide protection for the wiring on the surface of the circuit board from the environment. Regarding claim 2, Sugiyama discloses the claimed invention as set forth in claim 1. Sugiyama further suggests the flexible substrate includes a tapered signal line (331a, Fig. 3) that is formed on the first surface and joins the signal line with the signal pad, the tapered signal line having a width varying in a tapered shape, and the first protrusion part covers the signal line and at least a part of the tapered signal line (Fig. 3). Regarding claim 3, Sugiyama discloses the claimed invention as set forth in claim 1. Sugiyama further suggests a substrate (PCB 110, Fig. 2) that is connected to the flexible substrate (130), wherein the substrate includes a signal electrode (311, Fig. 3) that is connected to the signal pad (321) of the flexible substrate, and a ground electrode (312) that is connected to the ground pad (322) of the flexible substrate, and a tip end of the ground electrode on the second component side is located closer to the second component than a tip end of the signal electrode on the second component side (the tip end of the signal wire 333 is a distance from the edge compared with the ground electrode tip 332 which is closer to the component 140 side). Regarding claim 4, Sugiyama discloses the claimed invention as set forth in claim 1. Sugiyama, in view of Muto, further suggests an outer surface shape of the first coverlay and an outer surface shape of the second coverlay have a same shape, and a coverlay is formed by joining the first coverlay with the second coverlay (Muto suggests that it is known in the art to have a coverlay on both surfaces of the circuit board. It is also known in the art to duplicate a known working component. In this case, it is obvious to duplicate a working coverlay for both surfaces of the circuit board). Regarding claim 5, Sugiyama discloses the claimed invention as set forth in claim 2. Sugiyama further suggests a tip end of the ground pattern on the first component side is located closer to the signal pad than a connection site where the tapered signal line and the signal line are connected (since the ground pattern 323 is wider than the signal line 333, the ground pattern is closer to signal pad 321; Fig. 3). Regarding claim 6, Sugiyama discloses the claimed invention as set forth in claim 1. Sugiyama further suggests a plurality of first through holes (via holes connecting top and bottom signal pads together, and also connected top and bottom ground pads together; paragraph 31) that penetrate through the signal pad, and a plurality of second through holes that penetrate through the ground pad, wherein among the second through holes, a second through hole farthest away from an end part on the first component side is located further away from the end part on the first component side than the first through hole. Regarding claim 7, Sugiyama discloses the claimed invention as set forth in claim 1. Sugiyama further suggests width of the ground pad (312, Fig. 3) is formed wider than width of the signal pad (311). Regarding claim 8, Sugiyama discloses the claimed invention as set forth in claim 1. Sugiyama further suggests the ground pad has a configuration in which a width of the ground pad is increased such that a gap between the ground pad and the signal pad approaches continuously from an end part on the first component side toward the second component side (the size ground pad increases to a larger than the size of the signal pad). Regarding claim 9, Sugiyama discloses the claimed invention as set forth in claim 8. Sugiyama further suggests a plurality of first through holes (via holes connecting top and bottom signal pads together, and also connected top and bottom ground pads together; paragraph 31) that penetrate through the signal pad, and a plurality of second through holes (the through holes near components 140) that penetrate through the ground pad, wherein among the second through holes, a second through hole farthest away from an end part on the first component side is located further away from the end part on the first component side than the first through hole (the through holes near component 140 are far away from the component 120). Regarding claim 10, Sugiyama discloses the claimed invention as set forth in claim 1. Sugiyama further suggests the signal line is a signal line that transmits a high-frequency electrical signal (paragraphs 7, 11). Regarding claim 11, Sugiyama discloses an optical transmission device, comprising: an optical modulator (an optical modulator 120) that is configured to optically modulate light according to an electrical signal (an inherent function of an optical modular); a driver (a driver 140) that is configured to output the electrical signal; and a flexible substrate (FPC 130) that electrically connects the optical modulator and the driver, wherein the flexible substrate includes a signal pad (321, 331) at least a part of which is fixed to the driver (the pads on the driver side 140 is fixed on the driver 140, Fig. 2, through the connection on substrate 110), a ground pad (322, 332) at least a part of which is fixed to the driver (the pads on the driver side 140 is fixed on the driver 140, Fig. 2, through the connection on substrate 110), a signal line (333) that is formed on a first surface (bottom surface of the FPC 130) of the flexible substrate and connects the signal pad and the optical modulator, the signal line having a width (331a) narrower than the signal pad (Fig. 3), a ground pattern (the grounding pattern 323) that is formed on a second surface (top surface of the FPC) serving as a rear surface of the first surface, a first coverlay (the coverlay 205) including a first protrusion part (the protrusion 205a) that is formed on the first surface, covers a region on the flexible substrate where the signal line (333) is disposed, and protrudes at a location (the location at 205a) where the signal pad is disposed, toward an end part of the flexible substrate on the driver side than the region where the signal line is disposed (the signal line is on the side of the component 120 and the pad 331 is toward the driver side). Sugiyama does not explicitly disclose a second coverlay including a second protrusion part that is formed on the second surface, protrudes at a location where the signal pad is disposed, toward an end part of the flexible substrate on the driver side, and covers a region on the ground pattern facing at least the signal pad. Muto suggests a coverlay layers (102, 106, 108) on both sides of the circuit board (100, Fig.8). Sugiyama suggests a protrusion (205a) on the overlay layer 205. It would have been obvious to one having skill in the art at the effective filing date of the invention to cover both surface of the circuit board and modify the shape of the coverlay layer in order to provide protection for the wiring on the surface of the circuit board from the environment. Regarding claim 12, Sugiyama discloses an optical reception device, comprising: an optical receiver (an optical modulator 120) that is configured to convert received light into an electrical signal (the inherent function of the optical modulator); a signal processor (the driver 140) that is configured to perform signal processing on the converted electrical signal (the inherent function of a driver to process the signal into driving instructions); and a flexible substrate (the FPC 130) that electrically connects the optical receiver and the signal processor, wherein the flexible substrate includes a signal pad (321, 331) at least a part of which is fixed to the signal processor, a ground pad (322, 332) at least a part of which is fixed to the signal processor, a signal line (333) that is formed on a first surface (bottom surface) of the flexible substrate and connects the signal pad and the optical receiver, the signal line having a width narrower (331a) than the signal pad, a ground pattern (323) that is formed on a second surface serving as a rear surface of the first surface, a first coverlay (205) including a first protrusion part (331a) that is formed on the first surface, covers a region on the flexible substrate where the signal line is disposed, and protrudes at a location where the signal pad is disposed, toward an end part of the flexible substrate on the signal processor side than the region where the signal line is disposed (the signal line is on the side of the component 120 and the pad 331 is toward the driver side). Sugiyama does not explicitly disclose a second coverlay including a second protrusion part that is formed on the second surface, protrudes at a location where the signal pad is disposed, toward an end part of the flexible substrate on the signal processor side, and covers a region on the ground pattern facing at least the signal pad. Muto suggests a coverlay layers (102, 106, 108) on both sides of the circuit board (100, Fig.8). Sugiyama suggests a protrusion (205a) on the overlay layer 205. It would have been obvious to one having skill in the art at the effective filing date of the invention to cover both surface of the circuit board and modify the shape of the coverlay layer in order to provide protection for the wiring on the surface of the circuit board from the environment. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ogiso (US 12176959) discloses two components connected to each other through a flexible circuit board (450, Fig. 4). Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH B TRAN whose telephone number is (571)272-9289. The examiner can normally be reached M-F 8:00 AM - 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BINH B TRAN/Primary Examiner, Art Unit 2848
Read full office action

Prosecution Timeline

May 16, 2024
Application Filed
Feb 06, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
92%
With Interview (+12.4%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 680 resolved cases by this examiner. Grant probability derived from career allow rate.

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