Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to applicant’s communication filed on 05/16/24. Claims 1-19 are pending in this application.
Information Disclosure Statement
The information disclosure statement filed on 05/16/24 has been received and is being considered.
Claim Rejections Under 35 U.S.C. §102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-19 are rejected under 35 U.S.C. §102(a)(1) and §102(a)(2) as being unpatentable over Liu (US 20220384610 A1).
Regarding claim 1, Liu discloses a semiconductor device, comprising: a first channel sheet located over a lower structure and extending in a first direction; a gate layer covering a portion of the first channel sheet when coinciding with the first channel sheet in a second direction (fig 16 disclosing gate 2080 and 250a), the second direction being perpendicular to the first direction (see horizontal vs vertical); and a gate insulating layer located between the first channel sheet and the gate layer (252 gate dielectric between 2080 and 256); wherein the first channel sheet has a half-pipe structure including a curved surface in the second direction (see fig 14, disclosing 1080 has concave shape).
Regarding claim 2, Liu discloses the semiconductor device of claim 1, wherein an upper surface of the lower structure has a half-pipe structure extending in the first direction and curved in the second direction (see fig 14 disclosing curved channel regions, 2080).
Regarding claim 3, Liu discloses the semiconductor device of claim 1, further comprising a second channel sheet and a third channel sheet located over the first channel sheet and arranged in a third direction, the third direction being perpendicular to both the first direction and the second direction(see fig 14 disclosing curved channel regions, 2080 disclosing at least three channels).
Regarding claim 4, Liu discloses the semiconductor device of claim 3, wherein the second and third channel sheets have a same structure as the first channel sheet(see fig 14 disclosing curved channel regions, 2080 disclosing same structures).
Regarding claim 5, Liu discloses the semiconductor device of claim 3, wherein the gate layer covers a portion of the second channel sheet and a portion of the third channel sheet (see fig 16 disclosing 250 between channel layers).
Regarding claim 6, Liu discloses the semiconductor device of claim 3, wherein the gate layer covers a portion of an upper surface, a portion of a lower surface, and a portion of each side surface of each of the second and third channel sheets in the second direction (see fig 14 disclosing curved channel regions, 2080 with gate 250 between layers).
Regarding claim 7, Liu discloses the semiconductor device of claim 1, wherein the gate layer covers a portion of an upper surface and a portion of each side surface of the first channel sheet in the second direction(see fig 14 disclosing curved channel regions, 2080 with gate 250 between layers).
Regarding claim 8, Liu discloses the semiconductor device of claim 1, wherein the gate layer covers a portion of an upper surface, a portion of a lower surface, and a portion of each side surface of the first channel sheet in the second direction(see fig 14 disclosing curved channel regions, 2080 with gate 250 between layers).
Regarding claim 9, Liu discloses the semiconductor device of claim 1, wherein an upper surface and a lower surface of a cross section of the first channel sheet in the first direction form a flat surface, and wherein an upper surface and a lower surface of a cross-section of the first channel sheet form a curved surface in the second direction, (see fig 14 disclosing curved channel regions, 2080 with gate 250 between layers).
Regarding claim 10, Liu discloses the semiconductor device of claim 1, wherein the first channel sheet has a curved cross-section in the second direction, and wherein the curved cross-section of the first channel sheet is concave based on the curved cross-section being between a focus and the lower structure(see fig 14 disclosing curved channel regions, 2080 with gate 250 between layers and the curves are concave).
Regarding claim 11, Liu discloses a method of manufacturing a semiconductor device, the method comprising: etching a portion of a lower structure such that an upper surface of the lower structure has a half-pipe structure extending in a first direction and curved in a second direction (see figs 13-14 disclosing etching curve), the second direction being perpendicular to the first direction (horizontal and vertical); forming a first channel sheet 2080 over the lower structure to have a similar curvature to the upper surface of the lower structure (see 2080’s have curvature); forming a gate insulating layer that covers the first channel sheet (252 insulating 256 from 2080); and
forming a gate layer that covers a portion of the first channel sheet with the gate insulating layer interposed therebetween (see fig 14, where channel 2080 with gate 150 covers it).
Regarding claim 12, Liu discloses the method of claim 11, wherein the etching of the portion of the lower structure further comprises etching the portion of the lower structure so that the upper surface of the lower structure extends linearly in the first direction and curves in the second direction (see fig 14 disclosing etching), and wherein the upper surface of the lower structure is concave in the second direction based on the upper surface of the lower structure being between a focus and a lower surface of the lower structure(see fig 14 disclosing curved channel regions, 2080 with gate 250 between layers and the curves are concave).
Regarding claim 13, Liu discloses the method of claim 11, further comprising, before the forming of the first channel sheet, forming an insulating layer contacting the upper surface of the lower structure, wherein the insulating layer is formed to have a similar curvature to the upper surface of the lower structure(see fig 14 disclosing curved channel regions, 2080 with gate 250 between layers and the curves are concave).
Regarding claim 14, Liu discloses the method of claim 11, wherein the forming of the first channel sheet is performed simultaneously with forming a second channel sheet and a third channel sheet that are located over the first channel sheet and arranged in a third direction, the third direction being perpendicular to both the first and second directions (see fig 14 disclosing simultaneous formation of 2080).
Regarding claim 15, Liu discloses the method of claim 14, wherein the forming of the first to third channel sheets comprises: alternately stacking preliminary channel layers and sacrificial layers over the lower structure; and etching a portion of each of the preliminary channel layers and removing the sacrificial layers to form the first to third channel sheets (see figs 12-14 disclosing alternate arrangement and etching).
Regarding claim 16, Liu discloses the method of claim 14, wherein the forming of the gate layer comprises forming the gate insulating layer to cover the second to third channel sheets (see fig 14 disclosing curved channel regions, 2080 with gate 250 between layers and the curves are concave).
Regarding claim 17, Liu discloses the method of claim 14, wherein the forming of the gate layer comprises forming the gate layer that covers a portion of an upper surface, a portion of a lower surface, and a portion of each side surface of each of the second and third channel sheets in the second direction(see fig 14 disclosing curved channel regions, 2080 with gate 250 between layers and the curves are concave).
Regarding claim 18, Liu discloses the method of claim 11, wherein the forming the gate layer comprises forming the gate layer that covers a portion of an upper surface and a portion of each side surface of the first channel sheet in the second direction(see fig 14 disclosing curved channel regions, 2080 with gate 250 between layers and the curves are concave).
Regarding claim 19, Liu discloses the method of claim 11, wherein the forming the gate layer comprises forming the gate layer that covers a portion of an upper surface, a portion of a lower surface, and a portion of each side surface of the first channel sheet in the second direction(see fig 14 disclosing curved channel regions, 2080 with gate 250 between layers and the curves are concave).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EDWARD CHIN/Primary Examiner, Art Unit 2893
Prosecution Insights