CTNF 18/666,358 CTNF 77467 DETAILED ACTION 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Objections Claims 2, 4, 5, 6, 10, 11, 15 and 17 are objected to because of the following informalities: Claim 2 recites the limitation “wherein the control gate includes a length in a direction perpendicular to a direction between first and second memory cell strings ” in lines 1-2. However, there a lack of proper antecedent basis for “first and second memory cell strings” in the claim. Changing “first and second memory cell strings” to --the first memory cell string and the second memory cell string-- provides proper antecedent basis and consistency throughout the claim. Claim 4 recites the limitation “data line associated with the first and second memory cell strings ” in lines 1-2. However, there a lack of proper antecedent basis for “the first and second memory cell strings” in the claim. Changing “the first and second memory cell strings” to --the first memory cell string and the second memory cell string-- provides proper antecedent basis and consistency throughout the claim. Claim 11 recites the limitation “ the first and second memory cell string are located over the conductive region” in lines 3-4. However, there a lack of proper antecedent basis for “the first and second memory cell string” in the claim. Changing “the first and second memory cell string” to -- the first memory cell string and the second memory cell string-- provides proper antecedent basis and consistency throughout the claim. Claim 15 recites the limitation “wherein the first and second control gates are further configured to select the first, second, and third memory cells in an erase operation” in lines 1-3. However, there is a lack of proper antecedent basis for “the first and second control gates” and “the first, second, and third memory cells” in the claim. Changing “the first and second control gates” and “the first, second, and third memory cells” to --the first control gate and the second control gate-- and --the first memory cell, the second memory cell, and the third memory cell-- provides proper antecedent basis and consistency throughout the claim. Claim 17 recites the limitation “circuitry to apply different voltages to the first, second, and third data line during the first read operation” in lines 1-2. However, there is a lack of proper antecedent basis for “the first, second, and third data line” in the claim. Chaing “the first, second, and third data line” to -- the first data line, the second data lime, and third data line-- provides proper antecedent basis and consistency throughout the claim. Applicant’s cooperation is requested in reviewing the claims’ structure to ensure proper claim construction and to correct any subsequently discovered instances of claim language noncompliance. See Morton International Inc. , 28USPQ2d 1190, 1195 (CAFC, 1993). Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Thong et al. (US 2022/0199467) . Re Claim 1, Thong et al. disclose an apparatus comprising: a first memory cell string (230a) including a first channel structure (not labeled) a first charge storage structure, and a first dielectric structure between the first channel structure (430) and the first charge storage structure (not labeled, see Fig. 3 and Paragraphs [0050] and [0076]); a second memory cell string(232a, Paragraph [0050]) adjacent the first memory cell string (see Fig. 3), the second memory cell string including (232a) a second channel structure (i.e., 2 nd 430), a second charge storage structure (not labeled), and a second dielectric structure between the second channel structure and the second charge storage structure (see Figs. 3 and 4A); and a control gate (220 221 222 223, Paragraph [0065])) separated from the first charge storage structure by a third dielectric structure and separated from the second channel structure by a fourth dielectric structure (see fig. 4a), wherein the control gate and the first charge storage structure are between the first channel structure and the second channel structure (see Figs. 3 and 4A and related text in Paragraphs [0050] – [0083]). Re Claim 2, as applied to claim 1 above, Thong et al. disclose all the claimed limitations including wherein the control gate (220 221 222 223) includes a length in a direction perpendicular to a direction between first and second memory cell strings (see Fig. 4A). Re Claim 3, as applied to claim 1 above, Thong et al. disclose all the claimed limitations including a first data line associated with the first memory cell string; and a second data line associated with the second memory cell string. Re Claim 4, as applied to claim 1 above, Thong et al. disclose all the claimed limitations including a data line (270) associated with the first and second memory cell strings (Fig, 4A and Paragraph [0063]). Re Claim 5, as applied to claim 1 above, Thong et al. disclose all the claimed limitations including wherein the first memory cell string includes a first additional charge storage structure; and wherein the first charge storage structure is configured to store information in a first memory cell of the first memory cell string; and the first additional charge storage structure is configured to store information in a second memory cell of the first memory cell string, and the charge storage structure and additional charge storage structure are separated from each other by a dielectric material (see Figs. 3 and 4A and related text in Paragraphs [0050] – [0083]). Re Claim 6, as applied to claim 1 above, Thong et al. disclose all the claimed limitations including wherein the first memory cell string includes a first additional charge storage structure; and wherein the first charge storage structure is configured to store information in a first memory cell of the first memory cell string; and the first additional charge storage structure is configured to store information in a second memory cell of the first memory cell string, and the charge storage structure and additional charge storage structure are part of a continuous piece of material (see Figs. 3 and 4A and related text in Paragraphs [0050] – [0083]). Re Claim 7, as applied to claim 1 above, Thong et al. disclose all the claimed limitations including wherein the charge storage structure includes a polysilicon material (see Figs. 3 and 4A and related text in Paragraphs [0050] – [0083]). Re Claim 8, as applied to claim 1 above, Thong et al. disclose all the claimed limitations including wherein the charge storage structure includes a dielectric material (see Figs. 3 and 4A and related text in Paragraphs [0050] – [0083]). Re Claim 9, as applied to claim 1 above, Thong et al. disclose all the claimed limitations including wherein the charge storage structure includes a metal material (see Figs. 3 and 4A and related text in Paragraphs [0050] – [0083]). Re Claim 10, Thong et al. disclose an apparatus comprising: a conductive region (290); a first memory cell string (230a) including a first channel structure (430) coupled to the conductive region, and first charge storage structures along the first channel structure (430) and separated from the first channel structure by a first dielectric structure (see Fig. 4A); a second memory cell string (232a) including a second channel structure (430) coupled to the conductive region, and second charge storage structures along the second channel structure and separated from the first channel structure by a second dielectric structure (see Fig. 4A); control gates (220 221 222 223) associated with the first memory cells and the second memory cell (Fig. 4A), the control gates located one over another in the conductive region and between the first and second memory strings (Fig. 4A); a third dielectric structure including a first side adjacent the first charge storage structures and a second side adjacent the control gates; and a fourth dielectric structure including a first side adjacent the control gates and a second side adjacent the second channel structure (see Figs. 3 and 4A and related text in Paragraphs [0050] – [0083]). Re Claim 11, as applied to claim 10 above, Thong et al. disclose all the claimed limitations including a substrate (499), wherein: the conductive region (290 495) is located over the substrate (499); and the first and second memory cell string are located over the conductive region structure (see Figs. 3 and 4A and related text in Paragraphs [0050] – [0083]). Re Claim 12, as applied to claim 10 above, Thong et al. disclose all the claimed limitations including wherein each of the control gates includes a length in a direction perpendicular to a direction between first and second channel structures (see Figs. 3 and 4A and related text in Paragraphs [0050] – [0083]). Re Claim 13, as applied to claim 10 above, Thong et al. disclose all the claimed limitations including the first dielectric structure is configured to facilitate tunneling of charge between the first charge storage structures and the first channel structure; and the second dielectric structure is configured to facilitate tunneling of charge between the second charge storage structures and the second channel structure (see Figs. 3 and 4A and related text in Paragraphs [0050] – [0083]). Re Claim 14, Thong et al. disclose an apparatus comprising: a first memory cell included in a first memory cell string (230a); a second memory cell included in a second memory cell string (232a); a third memory cell included in a third memory cell string (234a); a first control gate to select the first memory cell in a first write operation and to select the second memory cell in a first read operation; a second control gate to select the second memory cell in a second write operation and to select the third memory cell in a second read operation (see Figs. 3 and 4A and related text in Paragraphs [0050] – [0083]). Re Claim 15, as applied to claim 14 above, Thong et al. disclose all the claimed limitations including wherein the first and second control gates are further configured to select the first, second, and third memory cells in an erase operation (see Figs. 3 and 4A and related text in Paragraphs [0050] – [0083]). Re Claim 16, as applied to claim 14 above, Thong et al. disclose all the claimed limitations including a first data line associated with the first memory cell string; a second data line associated with the second memory cell string; and a third data line associated with the third memory cell string (see Figs. 3 and 4A and related text in Paragraphs [0050] – [0083]). Re Claim 17, as applied to claim 16 above, Thong et al. disclose all the claimed limitations including circuitry to apply different voltages to the first, second, and third data line during the first read operation (see Figs. 3 and 4A and related text in Paragraphs [0050] – [0083]). Re Claim 18. as applied to claim 16 above, Thong et al. disclose all the claimed limitations including circuitry to place the third data line in a float condition during the first write operation (see Figs. 3 and 4A and related text in Paragraphs [0050] – [0083]). Re Claim 19, as applied to claim 14 above, Thong et al. disclose all the claimed limitations including a data line associated with the first, second, and third memory cell strings (see Figs. 3 and 4A and related text in Paragraphs [0050] – [0083]). Re Claim 20, as applied to claim 19 above, Thong et al. disclose all the claimed limitations including circuitry to place the data line in one of a float condition and ground potential during an erase operation (see Figs. 3 and 4A and related text in Paragraphs [0050] – [0083]) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure SHIN et al. (US 2016/0343729), LEE et al. (US 2017/0194057), Futatsuyama et al. (US 2020/0027511) and Lin et al. (US 2023/0031362) also disclose similar inventive subject matter . Correspondence Any inquiry concerning this communication or earlier communications from the examiner should be directed to BROOK KEBEDE whose telephone number is 571-272-1862. The examiner can normally be reached Monday Friday 8:00 AM 5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BROOK KEBEDE/ Primary Examiner, Art Unit 2894 /BK/ June 12, 2026 Application/Control Number: 18/666,358 Page 2 Art Unit: 2818 Application/Control Number: 18/666,358 Page 3 Art Unit: 2818 Application/Control Number: 18/666,358 Page 4 Art Unit: 2818 Application/Control Number: 18/666,358 Page 5 Art Unit: 2818 Application/Control Number: 18/666,358 Page 6 Art Unit: 2818 Application/Control Number: 18/666,358 Page 7 Art Unit: 2818 Application/Control Number: 18/666,358 Page 8 Art Unit: 2818 Application/Control Number: 18/666,358 Page 9 Art Unit: 2818
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