DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LEE et al. (U.S 2015/0035148 A1) (submitted by the Applicant from the IDS filed on 06/04/2024).
As to claim 1, LEE et al. disclose in Fig. 3 an apparatus, comprising:
a first semiconductor device package (“upper package” 200) including a first semiconductor die (“upper semiconductor chip” 220) attached to an interposer substrate (“upper package substrate” 210) that comprises a plurality of terminals (“solder pads” 213) (Fig. 3, para. [0048]-[0050]);
and a second semiconductor device package (“lower package” 100) coupled with the first semiconductor device package (“upper package” 200) (Fig. 3, para. [0048]) and including: a second semiconductor die (“lower semiconductor chip” 120) attached to a die-attach region (see a region having elements 117 on the bottom surface of chip 120, Fig. 3) of a base substrate (“interconnection part” 101) (Fig. 3, para. [0044], [0062]-[0063]);
a plurality of stratum of matrix material {comprising an insulating layer having elements 117, a “core part” 103 that may be formed of “epoxy molding compound (EMC)”, and “insulating cover” 105, Fig. 3, para. [0059]. [0063]} over a perimeter region (peripheral region) of the base substrate (“interconnection part” 101) that surrounds the die-attach region (see a region having elements 117 on the bottom surface of chip 120, Fig. 3) (Fig. 3, para. [0059], [0063]); and
an interconnect array (comprising “core part” 103, “connection vias” 115, “solder balls” 215 and “intermetallic compound layer” 217), over the perimeter region (peripheral region) (Fig. 3, para. [0069]-[0070]), comprising a plurality of interconnects (comprising each individual stack of “connection vias” 115, “solder balls” 215 and “intermetallic compound layer” 217) each electrically coupled with a corresponding terminal (“solder pads” 213) of the interposer substrate (“upper package substrate” 210) (Fig. 3, para. [0067]), wherein each interconnect (comprising a stack of “connection vias” 115, “solder balls” 215 and “intermetallic compound layer” 217) comprises multiple stacked interconnect segments (each individual stack of 115, 215 & 217) each of which extends through a respective stratum (see an insulating layer having elements 117, and each layer 103, and 105) of the plurality of stratum of matrix material {comprising an insulating layer having elements 117, a “core part” 103, and “insulating cover” 105, Fig. 3, para. [0059], [0063]} (see Fig. 3, para. [0051]-[0052]).
As to claim 2, as applied to claim 1 above, LEE et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein a bottom surface of the second semiconductor die (“lower semiconductor chip” 120) comprises a plurality of electrical connectors (“chip vias” 117) coupled with a top surface of the base substrate (“interconnection part” 101) (Fig. 3, para. [0044]), and wherein a top surface of the second semiconductor die (“lower semiconductor chip” 120) is at a first height above the top surface of the base substrate (“interconnection part” 101) (see Fig. 3).
As to claim 3, as applied to claims 1 and 2 above, LEE et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein each interconnect (comprising a stack of “connection vias” 115, “solder balls” 215 and “intermetallic compound layer” 217) extends from the top surface of the base substrate (“interconnection part” 101) to a second height greater than the first height (see Fig. 3).
As to claim 4, as applied to claims 1 and 2 above, LEE et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein the second semiconductor die (“lower semiconductor chip” 120) is electrically coupled with a second plurality of electrical connectors (“outer terminals” 107) on a bottom surface of the base substrate (“interconnection part” 101) (Fig. 3, para. [0047]).
As to claim 5, as applied to claim 1 above, LEE et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein each interconnect (comprising a stack of “connection vias” 115, “solder balls” 215 and “intermetallic compound layer” 217) in the plurality of interconnects (comprising each individual stack of “connection vias” 115, “solder balls” 215 and “intermetallic compound layer” 217) is electrically isolated from each other interconnect (comprising other stack of “connection vias” 115, “solder balls” 215 and “intermetallic compound layer” 217) in the plurality of interconnects (comprising each individual stack of “connection vias” 115, “solder balls” 215 and “intermetallic compound layer” 217) (see Fig. 3, at least an interconnect from the right side of the structure is electrically isolated from at least an interconnect from the left side of the structure).
As to claim 6, as applied to claim 1 above, LEE et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein the first semiconductor die (“upper semiconductor chip” 220) comprises a plurality of electrical connectors (comprising 222 & 223) electrically coupled with the plurality of terminals (“solder pads” 213) (Fig. 3, para. [0050]).
As to claim 7, as applied to claims 1 and 6 above, LEE et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein the first semiconductor die (“upper semiconductor chip” 220) is electrically connected to the second semiconductor die (“lower semiconductor chip” 120) through the plurality of electrical connectors (comprising 222 & 223), the plurality of terminals (“solder pads” 213), and the plurality of interconnects (comprising each individual stack of “connection vias” 115, “solder balls” 215 and “intermetallic compound layer” 217) (Fig. 3, para. [0040][0050]).
As to claim 8, as applied to claim 1 above, LEE et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein each segment (115/215/217) is conically shaped (Fig. 3).
As to claim 9, LEE et al. disclose in Fig. 3 an apparatus, comprising:
a first semiconductor device package (“upper package” 200) including a first semiconductor die (“upper semiconductor chip” 220) attached to an interposer substrate (“upper package substrate” 210) that comprises a terminal (“solder pad” 213) (Fig. 3, para. [0048]-[0050]); and
a second semiconductor device package (“lower package” 100) coupled with the first semiconductor device package (“upper package” 200) (Fig. 3, para. [0048]) and including: a second semiconductor die (“lower semiconductor chip” 120) attached to a die-attach region (see a region having elements 117 on the bottom surface of chip 120, Fig. 3) of a base substrate (“interconnection part” 101) (Fig. 3, para. [0044], [0062]-[0063]);
a plurality of stratum of matrix material {comprising an insulating layer having elements 117, a “core part” 103 that may be formed of “epoxy molding compound (EMC)”, and “insulating cover” 105, Fig. 3, para. [0059]. [0063]} over a perimeter region (peripheral region) of the base substrate (“interconnection part” 101) that surrounds the die-attach region (see a region having elements 117 on the bottom surface of chip 120, Fig. 3) (Fig. 3, para. [0059], [0063]);
and an interconnect (comprising a stack of “connection vias” 115, “solder balls” 215 and “intermetallic compound layer” 217), over the perimeter region (peripheral region) (Fig. 3, para. [0069]-[0070]), coupled with the terminal of the interposer substrate (“upper package substrate” 210) and comprising multiple stacked interconnect segments (each individual stack of 115, 215 & 217) each of which extends through a respective stratum (see an insulating layer having elements 117, and each layer 103, and 105) of the plurality of stratum of matrix material {comprising an insulating layer having elements 117, a “core part” 103, and “insulating cover” 105, Fig. 3, para. [0059], [0063]} (see Fig. 3, para. [0051]-[0052]).
As to claim 10, as applied to claim 9 above, LEE et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein a bottom surface of the second semiconductor die (“lower semiconductor chip” 120) comprises a plurality of electrical connectors (“chip vias” 117) coupled with a top surface of the base substrate (“interconnection part” 101) (Fig. 3, para. [0044]), and wherein a top surface of the second semiconductor die (“lower semiconductor chip” 120) is at a first height above the top surface of the base substrate (“interconnection part” 101) (see Fig. 3).
As to claim 11, as applied to claims 9 and 10 above, LEE et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein each interconnect (comprising a stack of “connection vias” 115, “solder balls” 215 and “intermetallic compound layer” 217) extends from the top surface of the base substrate (“interconnection part” 101) to a second height greater than the first height (see Fig. 3).
As to claim 12, as applied to claims 9 and 10 above, LEE et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein the second semiconductor die (“lower semiconductor chip” 120) is electrically coupled with a second plurality of electrical connectors (“outer terminals” 107) on a bottom surface of the base substrate (“interconnection part” 101) (Fig. 3, para. [0047]).
As to claim 13, as applied to claim 9 above, LEE et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein the first semiconductor die (“upper semiconductor chip” 220) comprises an electrical connector (comprising 222 & 223) electrically coupled with the terminal (“solder pad” 213) (Fig. 3, para. [0050]).
As to claim 14, as applied to claims 9 and 13 above, LEE et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein the first semiconductor die (“upper semiconductor chip” 220) is electrically connected to the second semiconductor die (“lower semiconductor chip” 120) through the electrical connector (comprising 222 & 223), the terminal (“solder pad” 213), and the interconnect (comprising a stack of “connection vias” 115, “solder balls” 215 and “intermetallic compound layer” 217) (Fig. 3, para. [0040], [0050]).
As to claim 15, as applied to claim 9 above, LEE et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein each segment (115/215/217) is conically shaped (Fig. 3).
As to claim 16, LEE et al. disclose in Fig. 3 an apparatus, comprising:
a first semiconductor die (“upper semiconductor chip” 220) attached to an interposer substrate (“upper package substrate” 210) that comprises a plurality of terminals (“solder pads” 213) (Fig. 3, para. [0048]-[0050]);
a second semiconductor die (“lower semiconductor chip” 120) attached to a die-attach region (see a region having elements 117 on the bottom surface of chip 120, Fig. 3) of a base substrate (“interconnection part” 101) below the interposer substrate (“upper package substrate” 210) (Fig. 3, para. [0044], [0062]-[0063]);
a plurality of stratum of matrix material {comprising an insulating layer having elements 117, a “core part” 103 that may be formed of “epoxy molding compound (EMC)”, and “insulating cover” 105, Fig. 3, para. [0059]. [0063]} over a perimeter region (peripheral region) of the base substrate (“interconnection part” 101) that surrounds the die-attach region (see a region having elements 117 on the bottom surface of chip 120, Fig. 3) (Fig. 3, para. [0059], [0063]); and
an interconnect array (comprising “core part” 103, “connection vias” 115, “solder balls” 215 and “intermetallic compound layer” 217), over the perimeter region (peripheral region) (Fig. 3, para. [0069]-[0070]), comprising a plurality of interconnects (comprising each individual stack of “connection vias” 115, “solder balls” 215 and “intermetallic compound layer” 217) each electrically coupled with a corresponding terminal (“solder pads” 213) of the interposer substrate (“upper package substrate” 210) (Fig. 3, para. [0067]), wherein each interconnect (comprising a stack of “connection vias” 115, “solder balls” 215 and “intermetallic compound layer” 217) comprises multiple stacked interconnect segments (each individual stack of 115, 215 & 217) each of which extends through a respective stratum (see an insulating layer having elements 117, and each layer 103, and 105) of the plurality of stratum of matrix material {comprising an insulating layer having elements 117, a “core part” 103, and “insulating cover” 105, Fig. 3, para. [0059], [0063]} (see Fig. 3, para. [0051]-[0052]).
As to claim 17, as applied to claim 16 above, LEE et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein a bottom surface of the second semiconductor die (“lower semiconductor chip” 120) comprises a plurality of electrical connectors (“chip vias” 117) coupled with a top surface of the base substrate (“interconnection part” 101) (Fig. 3, para. [0044]), and wherein a top surface of the second semiconductor die (“lower semiconductor chip” 120) is at a first height above the top surface of the base substrate (“interconnection part” 101) (see Fig. 3); and wherein each interconnect (comprising a stack of “connection vias” 115, “solder balls” 215 and “intermetallic compound layer” 217) extends from the top surface of the base substrate (“interconnection part” 101) to a second height greater than the first height (see Fig. 3).
As to claim 18, as applied to claim 16 above, LEE et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein a bottom surface of the second semiconductor die (“lower semiconductor chip” 120) comprises a plurality of electrical connectors (“chip vias” 117) coupled with a top surface of the base substrate (“interconnection part” 101) (Fig. 3, para. [0044]), and wherein a top surface of, and wherein the second semiconductor die (“lower semiconductor chip” 120) is electrically coupled with a second plurality of electrical connectors (“outer terminals” 107) on a bottom surface of the base substrate (“interconnection part” 101) (Fig. 3, para. [0047]).
As to claim 19, as applied to claim 16 above, LEE et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein each interconnect (comprising a stack of “connection vias” 115, “solder balls” 215 and “intermetallic compound layer” 217) in the plurality of interconnects (comprising each individual stack of “connection vias” 115, “solder balls” 215 and “intermetallic compound layer” 217) is electrically isolated from each other interconnect (comprising other stack of “connection vias” 115, “solder balls” 215 and “intermetallic compound layer” 217) in the plurality of interconnects (comprising each individual stack of “connection vias” 115, “solder balls” 215 and “intermetallic compound layer” 217) (see Fig. 3, at least an interconnect from the right side of the structure is electrically isolated from at least an interconnect from the left side of the structure).
As to claim 20, as applied to claim 16 above, LEE et al. disclose in Fig. 3 all claimed limitations including the limitation: wherein the first semiconductor die (“upper semiconductor chip” 220) comprises a plurality of electrical connectors (comprising 222 & 223) electrically coupled with the plurality of terminals (“solder pads” 213) (Fig. 3, para. [0050]); and wherein the first semiconductor die (“upper semiconductor chip” 220) is electrically connected to the second semiconductor die (“lower semiconductor chip” 120) through the plurality of electrical connectors (comprising 222 & 223), the plurality of terminals (“solder pads” 213), and the plurality of interconnects (comprising each individual stack of “connection vias” 115, “solder balls” 215 and “intermetallic compound layer” 217) (Fig. 3, para. [0040][0050]).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 9 and 16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,139,229. Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations recited in claims 1, 9, and 16 of the present invention are recited within claim 1 of U.S. Patent No. 11,139,229 (submitted by the Applicant from the IDS filed on 06/04/2024).
Present application No. 18/666,369
U.S. Patent No. 11,139,229 (reference)
Claim 1: an apparatus, comprising: a first semiconductor device package including a first semiconductor die attached to an interposer substrate that comprises a plurality of terminals (“a second semiconductor device package having--an interposer substrate having a plurality of package terminals, …and a second semiconductor die attached to the interposer substrate”, see claim 1, lines 24-30, of U.S. Patent No. 11,139,229); and
a second semiconductor device package coupled with the first semiconductor device package and including: a second semiconductor die attached to a die-attach region of a base substrate (“a first semiconductor device package having …a first semiconductor die attached to the first side of the base substrate at the die-attach region”, see claim 1, lines 7-14 of U.S. Patent No. 11,139,229);
a plurality of stratum of matrix material over a perimeter region of the base substrate that surrounds the die-attach region (“an interconnect array over the perimeter region of the first side of the base substrate …wherein the interconnect array comprises a plurality of interconnect structures stacked on the first side of the base substrate, and wherein each individual interconnect structure includes a stratum of a matrix material and a plurality of interconnect segments arranged in a pattern of the interconnect array”, see claim 1, lines 15-23 of U.S. Patent No. 11,139,229); and
an interconnect array, over the perimeter region, comprising a plurality of interconnects each electrically coupled with a corresponding terminal of the interposer substrate, wherein each interconnect comprises multiple stacked interconnect segments each of which extends through a respective stratum of the plurality of stratum of matrix material (“an interconnect array over the perimeter region of the first side of the base substrate … wherein the interconnect array comprises a plurality of interconnect structures stacked on the first side of the base substrate, and wherein each individual interconnect structure includes a stratum of a matrix material and a plurality of interconnect segments arranged in a pattern of the interconnect array… wherein each individual package terminal is electrically coupled to a corresponding individual interconnect segment”, see claim 1, lines 15-28 of U.S. Patent No. 11,139,229).
Claim 1: a package-on-package system, comprising: a first semiconductor device package having-- a base substrate including a first side having a die-attach region and a perimeter region and a second side opposite the first side; a plurality of electrical connectors carried by the second side of the base substrate; a first semiconductor die attached to the first side of the base substrate at the die-attach region; and an interconnect array over the perimeter region of the first side of the base substrate and outside of the die-attach region, wherein the interconnect array comprises a plurality of interconnect structures stacked on the first side of the base substrate, and wherein each individual interconnect structure includes a stratum of a matrix material and a plurality of interconnect segments arranged in a pattern of the interconnect array; and a second semiconductor device package having--an interposer substrate having a plurality of package terminals, wherein each individual package terminal is electrically coupled to a corresponding individual interconnect segment; and a second semiconductor die attached to the interposer substrate.
Claim 9: an apparatus, comprising: a first semiconductor device package including a first semiconductor die attached to an interposer substrate that comprises a terminal (“a second semiconductor device package having--an interposer substrate having a plurality of package terminals, …and a second semiconductor die attached to the interposer substrate”, see claim 1, lines 24-30, of U.S. Patent No. 11,139,229);
and a second semiconductor device package coupled with the first semiconductor device package and including: a second semiconductor die attached to a die-attach region of a base substrate (“a first semiconductor device package having …a first semiconductor die attached to the first side of the base substrate at the die-attach region”, see claim 1, lines 7-14 of U.S. Patent No. 11,139,229);
a plurality of stratum of matrix material over a perimeter region of the base substrate that surrounds the die-attach region (“an interconnect array over the perimeter region of the first side of the base substrate …wherein the interconnect array comprises a plurality of interconnect structures stacked on the first side of the base substrate, and wherein each individual interconnect structure includes a stratum of a matrix material and a plurality of interconnect segments arranged in a pattern of the interconnect array”, see claim 1, lines 15-23 of U.S. Patent No. 11,139,229); and
an interconnect, over the perimeter region, coupled with the terminal of the interposer substrate and comprising multiple stacked interconnect segments each of which extends through a respective stratum of the plurality of stratum of matrix material (“an interconnect array over the perimeter region of the first side of the base substrate … wherein the interconnect array comprises a plurality of interconnect structures stacked on the first side of the base substrate, and wherein each individual interconnect structure includes a stratum of a matrix material and a plurality of interconnect segments arranged in a pattern of the interconnect array… wherein each individual package terminal is electrically coupled to a corresponding individual interconnect segment”, see claim 1, lines 15-28 of U.S. Patent No. 11,139,229).
Claim 1: a package-on-package system, comprising: a first semiconductor device package having-- a base substrate including a first side having a die-attach region and a perimeter region and a second side opposite the first side; a plurality of electrical connectors carried by the second side of the base substrate; a first semiconductor die attached to the first side of the base substrate at the die-attach region; and an interconnect array over the perimeter region of the first side of the base substrate and outside of the die-attach region, wherein the interconnect array comprises a plurality of interconnect structures stacked on the first side of the base substrate, and wherein each individual interconnect structure includes a stratum of a matrix material and a plurality of interconnect segments arranged in a pattern of the interconnect array; and a second semiconductor device package having--an interposer substrate having a plurality of package terminals, wherein each individual package terminal is electrically coupled to a corresponding individual interconnect segment; and a second semiconductor die attached to the interposer substrate.
Claim 16: an apparatus, comprising: a first semiconductor die attached to an interposer substrate that comprises a plurality of terminals (“a second semiconductor device package having--an interposer substrate having a plurality of package terminals, …and a second semiconductor die attached to the interposer substrate”, see claim 1, lines 24-30, of U.S. Patent No. 11,139,229);
a second semiconductor die attached to a die-attach region of a base substrate below the interposer substrate (“a first semiconductor device package having …a first semiconductor die attached to the first side of the base substrate at the die-attach region”, see claim 1, lines 7-14 of U.S. Patent No. 11,139,229);
a plurality of stratum of matrix material over a perimeter region of the base substrate that surrounds the die-attach region (“an interconnect array over the perimeter region of the first side of the base substrate …wherein the interconnect array comprises a plurality of interconnect structures stacked on the first side of the base substrate, and wherein each individual interconnect structure includes a stratum of a matrix material and a plurality of interconnect segments arranged in a pattern of the interconnect array”, see claim 1, lines 15-23 of U.S. Patent No. 11,139,229);; and
an interconnect array, over the perimeter region, comprising a plurality of interconnects each electrically coupled with a corresponding terminal of the interposer substrate, wherein each interconnect comprises multiple stacked interconnect segments each of which extends through a respective stratum of the plurality of stratum of matrix material (“an interconnect array over the perimeter region of the first side of the base substrate … wherein the interconnect array comprises a plurality of interconnect structures stacked on the first side of the base substrate, and wherein each individual interconnect structure includes a stratum of a matrix material and a plurality of interconnect segments arranged in a pattern of the interconnect array… wherein each individual package terminal is electrically coupled to a corresponding individual interconnect segment”, see claim 1, lines 15-28 of U.S. Patent No. 11,139,229).
Claim 1: a package-on-package system, comprising: a first semiconductor device package having-- a base substrate including a first side having a die-attach region and a perimeter region and a second side opposite the first side; a plurality of electrical connectors carried by the second side of the base substrate; a first semiconductor die attached to the first side of the base substrate at the die-attach region; and an interconnect array over the perimeter region of the first side of the base substrate and outside of the die-attach region, wherein the interconnect array comprises a plurality of interconnect structures stacked on the first side of the base substrate, and wherein each individual interconnect structure includes a stratum of a matrix material and a plurality of interconnect segments arranged in a pattern of the interconnect array; and a second semiconductor device package having--an interposer substrate having a plurality of package terminals, wherein each individual package terminal is electrically coupled to a corresponding individual interconnect segment; and a second semiconductor die attached to the interposer substrate.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: KIM et al. (U.S 2015/0287702 A1) disclose in Fig. 1 first and second semiconductor packages having first and second semiconductor chips (200, 1200), and an interconnect (1100) over the base substrate (1120).
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Thanh Y. Tran/Primary Examiner, Art Unit 2817 September 5, 2026
Prosecution Insights