DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 14:
The claim recites the element “a second substrate” at the end of the first limitation. This limitation lacks antecedent basis, as the claim 8 dependency chain only introduces a “substrate core” and not “a second substrate”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Raganathan (US 20190302379 A1) in view of Winzer (US 20230077979 A1).
Regarding claim 1:
Raganathan teaches a method of manufacturing an optical device (Figure 4, method of fabricating semiconductor packages with embedded optical die[s]), the method comprising:
forming a first metallization layer (Figure 3A, package substrate 302 with vias 306 and traces 304 formed in build up layers) adjacent to a first substrate (Figure 2, package 202 contains a core layer (substrate 212) that is the first substrate, upon which the metallization layer is formed in the remainder of 202 above 212);
embedding a first optical package within the first metallization layer (Figures 3B and 3C; cavity 312 which will contain the optical package is defined by removing a full thickness in portions of one or more build-up layers, optical die 322 is placed in cavity 312 and is the optical package);
Raganathan does not expressly claim that the die 322 is a package.
and forming a second metallization layer adjacent to the first optical package (Figure 3E, the interconnect layer 342 is formed overlying the optical die 322).
Winzer discloses a first optical package (Figure 1), namely an integrated optical communication device 210 comprising a photonic integrated circuit 214, an optical connector part 213 optically coupled to a first main surface 214_1 of the PIC 214 and EIC 215 mounted on substrate 211.
Before the effective filing date of the claimed invention, one of ordinary skill in the art would have found it obvious to modify the optical device described in the invention of Raganathan under the teachings of Winzer by replacing the embedded optical die with an optical package. A skilled artisan would find it obvious to modify the manufacturing process such that one may machine a cavity in the metallization layer which fits the assembled package, using methods, materials, and design oversight known to a skilled artisan. This would predictably result in a device where the metallization layer contains more than simple optical circuitry and improve the capability of opto-electronic function in the device.
Regarding claim 2:
Raganathan in view of Winzer teaches the method of claim 1, wherein:
the first substrate comprises first through substrate vias ([0023]: “Furthermore, the core of the semiconductor package may have a plurality of through vias to make electrical connections from one side of the core to the other side of the core.”).
Regarding claim 3:
Raganathan in view of Winzer teaches the method of claim 2, further comprising forming a third metallization layer on an opposite side of the first substrate from the first metallization layer.
Substrate 212 includes a core layer with one or more interconnect layers built up on one or both sides of the core layer (paragraphs 0022-0023). Build up layers may be fabricated on one or both sides of the package core.
Regarding claim 4:
Raganathan in view of Winzer teaches the method of claim 3, wherein at least one of the first though substrate vias is electrically connected to the first optical package.
Paragraph 49: interconnects (metal traces, vias) define electrical pathways for signals routed to and from the optical die and to the board. Electrical coupling to the optical die 204 is made through the electrical contacts on the top surface of the optical die by the way of the one or more overlying interconnect layers. The electrical pathway between the optical die and the board therefore passes through the through vias in the core.
Regarding claim 5:
Raganathan in view of Winzer teaches the method of claim 1, further comprising attaching a first semiconductor device to the second metallization layer.
Raganathan discloses attaching a first semiconductor device to the second metallization layer. The method includes assembling one or more integrated circuits over the second interconnect layer (paragraph 77). Electrical contacts 354, which may be solder bumps, are formed on the surface of the semiconductor package (Figure 3F, paragraph 42). Electronic components including integrated circuit dies are thereafter assembled onto the semiconductor using ordinary placement techniques, and attached by die-to-package interconnects 218 (Figure 2).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Raganathan (US 20190302379 A1) in view of Winzer (US 20230077979 A1), and further in view of Li (US 20230296854 A1).
Regarding claim 6:
Raganathan in view of Winzer teaches the method of claim 5.
Raganathan does not teach a first bridge device.
Li discloses embedding a bridge device within a metallization layer of a package substrate. Figures 1A-1C, paragraphs 10-11, teach that package substrates 102, 112, 122 each include embedded bridge circuitry 103, 113, and 123, that interconnects processing circuitry with a photonics integrated circuit and electronic integrated circuit. Similar bridge circuitry may be used to interconnect EICs to processing circuitry above a glass core (paragraph 19).
Before the effective filing date of the claimed invention, one of ordinary skill in the art would have found it obvious to modify the invention described in the rejection of claim 5 above under the teachings of Li to modify the metallization layer of the invention in claim 5 is further comprising embedding a first bridge device within the build-up interconnect layers of Raganathan. This may be accomplished using methods known to the art, with custom cavity making and pick and place sequences known to a skilled artisan, and would predictably result in fine-pitch electrical connections between the electronic components assembled on the package, which Li teaches is the function served by bridge circuity and adjacent redistribution layers (paragraph 19 of Li).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Raganathan (US 20190302379 A1) in view of Winzer (US 20230077979 A1), and further in view of Li (US 20230296854 A1) and Winterbottom (US 11835777 B2).
Regarding claim 7:
Raganathan in view of Winzer, and further in view of Li teaches the method of claim 6.
Raganathan is silent on second semiconductors.
Li teaches an optical device, further comprising:
attaching a second semiconductor device to the second metallization layer, wherein the second semiconductor device is electrically connected to the first semiconductor device through the first bridge device;
Package substrate 122 includes bridge circuitry 123 that interconnects processing circuitry (XPU) 124 with a photonics integrated circuit die 126 and an EIC 125, the XPU 124 and the EIC 125 disposed on top of the substrate 122 (Figure 1C). Paragraph 19 discloses that bridge circuitry similar to circuitries 103, 113, 123 to interconnect build up layers above the glass core (paragraph 19). Adding another semiconductor is a mere duplication of parts and the interconnect structure is explicitly taught in Li.
Li does not explicitly teach a third semiconductor layer as with the second, but the method for connecting to one is clear from the bridging circuitry, and a repeat of the method used to create the second layer would create a third.
Winterbottom teaches a third semiconductor device connected to a first semiconductor device through an optical package (Figure 4). Package 400 comprises a first die 410 and a second die 420 coupled to a substrate 440, together with an optical multi-die interconnect bridge 430 embedded in the substrate 440 (Figure 4). A portion of the first photonic transceiver 432 resides in first die 410 and another portion in OMIB 430; a portion of the second transceiver 434 and second photonic transceiver 434 is connected by photonic path 483. This shows a third semiconductor device attached to a second metallization layer.
Thus, Winterbottom teaches attaching a third semiconductor device to the second metallization layer, wherein the third semiconductor device is electrically connected to the first semiconductor device through the first optical package.
Before the effective filing date of the claimed invention, one of ordinary skill in the art would have found it obvious to modify the invention described in the rejection of claim 7 above under the teachings of Li and Winterbottom to attach a third semiconductor device to the invention and route its connection to a first semiconductor device on the invention of claim 7 as described in Raganathan. This may be accomplished using methods (deposition, etching, layering and machining techniques) known in the art, and would predictably result in die-to-die communication that is not constrained by pin count limitations and edge-of-chip reach of electrical interconnect.
Claim(s) 8-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 11982854 B2) in view of Raganathan (US 20190302379 A1), and further in view of Winzer (US 20230077979 A1).
Regarding claim 8:
Kim discloses a method of manufacturing an optical device (Title, abstract), the method comprising:
forming through substrate vias in a substrate core (Figures 5K-5L, holes 565 are formed through the interposer 560, and conductive material is deposited into the holes to form vias 570), the substrate core (560) having a rigidity of between about 51 GPa and about 320 GPa;
The instant application’s specification states:
“In particular embodiments the second substrate 1003 may be different from the first substrate 101 and may be formed of a material that can help prevent warpage, such as a material that has a high rigidity (e.g., a Young’s modulus of between about 51 GPa and 320 GPa) and a low coefficient of thermal expansion (e.g., a CTE range of between about 1 ppm/°C and about 8 ppm/°C). In particular embodiments the second substrate 1003 may be glass, aluminum oxide, ceramics, combinations of these, or the like. However, any suitable materials may be utilized. “
Kim describes their substrate core 560 as being a silicon dioxide glass. Per applicants’ disclosure, glass is a suitable material, and a skilled artisan would be aware that the Young’s modulus of silicon dioxide ranges between 60-73 GPa, which falls within the claimed range.
forming a first metallization layer on the substrate core, the first metallization layer comprising optical components (interposer 560 is );
forming a second metallization layer on an opposite side of the substrate core from the first metallization layer;
Kim discloses a redistribution layer 510 (second metallization layer) on the face of interposer 560 opposite the face bearing the optical waveguides 575 and photonic integrated circuit (opposite side of the substrate core), Figure 5A.
and attaching a first optical package to the first metallization layer; attaching a second optical package to the first metallization layer;
PIC 580 (first optical package) is attached to the interposer 560 (first metallization layer), PIC 585 is also attached to interposer 560 (Figure 5N).
Kim does not teach the first semiconductor device as claimed.
Raganathan discloses a build-up interconnect layer of a package substrate (first metallization layer) having vias 306 and traces 304 within a cavity 312 (Figure 3Bm paragraph 36),
and attaching a first semiconductor device to the first metallization layer (bottom cladding 332, core 334, and top cladding 336 forming an optical waveguide [optical components] are deposited and cured [Figure 3D, paragraph 52]).
Raganathan does not teach that the optical die is an optical package explicitly.
Winzer discloses a first optical package (Figure 1), namely an integrated optical communication device 210 comprising a photonic integrated circuit 214, an optical connector part 213 optically coupled to a first main surface 214_1 of the PIC 214 and EIC 215 mounted on substrate 211.
Before the effective filing date of the claimed invention, one of ordinary skill in the art would have found it obvious to modify the invention described in Kim under the teachings of Ramanathan and Winzer to include the claimed first metallization layer and an optical package in the cavity instead of a die. This may be accomplished using methods (deposition, etching, lasering) known to the art and materials known to the art, and would predictably result in a device which is efficiently integrated for low volumetric footprint and high throughput with minimal loss.
Regarding claim 9:
Kim in view of Raganathan and Winzer teach the method of claim 8, wherein the substrate core is a glass substrate.
Interposer 560 is a glass substrate, which may be silicon dioxide glass (“…the interposer-based PLC described herein are described as comprising glass, or silicon dioxide glass…”).
Regarding claim 10:
Kim in view of Raganathan and Winzer teach the method of claim 9, further comprising connecting a second semiconductor device (electrical component 216) to the first optical package (optical die 204) through the first metallization layer (package 202 is provided to the optical die via the one or more overlying interconnect layers to drive the optical die 204, see paragraph 29 and 75).
Regarding claim 11:
Kim in view of Raganathan and Winzer teach the method of claim 10.
Raganathan teaches that a semiconductor package may include both an optical die for transmitting optical signals generated by performing an electrical-to-optical conversion and an optical detector die to receive another optical signal and perform an optical-to electrical conversion (paragraph 49). Raganathan further teaches that interconnects define electrical pathways for signals routed to and from the optical die, to and from the electrical components mounted on the package, and to and from a board, and teaches two such electrical components (214, 216) assembled on the package (paragraph 21, Figure 2).
Raganathan does not expressly teach pairing a distinct third semiconductor device.
Kim teaches that EIC 110 (second semiconductor device) includes driver circuitry for an optical transmitter included in PIC 120 (first optical package) via electronic interconnects 135, and EIC 115 (third semiconductor device) includes driver circuitry for an optical receiver in PIC 125 (second optical package) via interconnects 135 (Figures 1A-1B).
Thus, Kim modifies the invention of claim 10 to be further comprising connecting a third semiconductor device to the second optical package through the first metallization layer.
Before the effective filing date of the claimed invention, one of ordinary skill in the art would have found it obvious to modify the invention described in the rejection of claim 10 above under the teachings of Kim to include a third semiconductor device. This may be accomplished using deposition, machining, and interconnection implementations understood in the art. Predictably, this would result in independent drive and receive channels, each EIC driving a corresponding PIC and improving the scalable function of the device.
Regarding claim 12:
Kim in view of Raganathan and Winzer teach the method of claim 11.
Kim does not teach high bandwidth in the third semiconductor explicitly.
Winterbottom teaches that the device in this position may be high bandwidth in memory.
Winterbottom teaches that the wafer 100 or the die 102 may include a memory device, and expressly lists a high bandwidth memory (HBM) among those devices. Winterbottom further teaches that when the memory is in a central region of the chip it requires extra distance for signals to travel when the memory is accessed the third semiconductor device is a high bandwidth memory. Winterbottom teaches that this positioning leads to more efficient processing (col 3).
Before the effective filing date of the claimed invention, one of ordinary skill in the art would have found it obvious to modify the invention described in the rejection of claim 11 under the teachings of Winterbottom to include high bandwidth memory in the optical device. This may be accomplished using placement techniques and components known in the art, and would predictably result in a device which can maintain performance with rising computational costs.
Regarding claim 13:
Kim in view of Raganathan and Winzer teach the method of claim 12, wherein the attaching the first optical package is performed at least in part with a reflow process.
Kim teaches that the solder 220 flows and solidified during the manufacturing process of attaching the PIC 120 to the interposer 105 (Figure 2, quote below).
“The under bump metal layer 265 may be shaped with an indentation in a middle region of the under bump metal layer 265 to aid in centering the solder 260 and interconnect bump 250 under the stacked via 235 as the solder 260 flows and solidifies during the manufacturing process of attaching the electronic integrated circuit 110 to the RDL 240.”
Regarding claim 14:
Kim in view of Raganathan and Winzer teach the method of claim 13, further comprising attaching the second metallization layer to a second substrate.
Figure 5G, Kim teaches C4 bump balls 545 attached to the second RDL 540 (second metallization layer) and teaches that the balls facilitate attaching the optoelectronic system as a multi-chip module to a PCB (second substrate).
Claim(s) 15, 16, 18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 20230296854 A1) in view of Winzer (US 20230077979 A1).
Regarding claim 15:
Li teaches an optical device (title, abstract) comprising:
an interposer substrate (Figure 2, package substrate 201);
and a first optical package embedded within the interposer substrate (PIC 208 embedded in the substrate), wherein
a first metallization layer of the interposer substrate is on a first side of the first optical package (build up layers 202 above the glass core 204),
a second metallization layer of the interposer substrate is on a second side of the first optical package (build up layers 206 below glass core 204),
and a glass core of the interposer substrate is disposed between the first metallization layer and the second metallization layer (glass core 204 sits between the metallization build up layers).
Li does not teach that the embedded optical component is a package.
Winzer discloses a first optical package (Figure 1), namely an integrated optical communication device 210 comprising a photonic integrated circuit 214, an optical connector part 213 optically coupled to a first main surface 214_1 of the PIC 214 and EIC 215 mounted on substrate 211.
Before the effective filing date of the claimed invention, one of ordinary skill in the art would have found it obvious to modify the optical device described in the invention of Li under the teachings of Winzer by replacing the embedded optical die with an optical package. A skilled artisan would find it obvious to modify the manufacturing process such that one may machine a cavity in the metallization layer which fits the assembled package, using methods, materials, and design oversight known to a skilled artisan. This would predictably result in a device where the metallization layer contains more than simple optical circuitry and improve the capability of opto-electronic function in the device.
Regarding claim 16:
Li in view of Winzer teaches the optical device of claim 15, wherein:
the first optical package is embedded within the glass core (PIC 208 is embedded in glass core 204, See Figure 2).
Regarding claim 18:
Li in view of Winzer teaches the optical device of claim 15, wherein:
Li does not teach a third metallization layer as claimed, directly.
Li teaches an optical component embedded within a metallization layer between the uppermost layer and the glass core (see rejection of claim 1 above), establishing this technique as known practice. As in paragraph 9, Li even teaches that a PIC is embedded in a package substrate at least two build-up layers above the core, placing the embedded PIC 126 within a metallization layer between the uppermost layer and the core (a third layer).
A skilled artisan would have found it obvious to duplicate the structure of the build up layers and embedded PICs in a third layer.
Raganathan expressly teaches this arrangement in detail.
the first optical package is embedded within (cavity 312) a third metallization layer between the first metallization layer and the glass core, with optical die 322 placed in one or more build-up layers (paragraph 36, Figure 3B).
Before the effective filing date of the claimed invention, one of ordinary skill in the art would have found it obvious to modify the invention described in the rejection of claim 15 above under the teachings of Raganathan to embed an optical package within a build-up metallization layer between the first metallization layer and the core. This may be accomplished using methods known to a skilled artisan, and would predictably result in a device with improved optical path length, optical coupling losses, number of operable optical interfaces, and cost efficiency with low volumetric footprint.
Regarding claim 20:
Li in view of Winzer teaches the optical device of claim 15.
Li teaches two semiconductor devices bonded to the first metallization layer (EIC 510 [first semiconductor device] and XPU 512 [second semiconductor device] on substrate 501, with RDLs 506 above the glass core 504 providing a fine-pitch electrical connection[s], Figures 5A-5B and paragraph 19).
Li does not teach the first semiconductor device being connected as claimed.
Winterbottom teaches a package 400 comprising a first die 410 and second die 420 coupled to a substrate 440 (and thus, a first semiconductor device and a second semiconductor device bonded to the first metallization layer), a portion of the first photonic transceiver 432 residing in the first die 410 and another portion in OMIB 430, and a portion of the second transceiver 434 residing in second die 420 and another in portion 430 (Figure 4). The bidirectional path 483 connecting the first transceiver 432 and the second photonic transceiver 434 establishes a through connection (thus, teaching the first semiconductor device connected to the second semiconductor device through the first optical package.)
Before the effective filing date of the claimed invention, one of ordinary skill in the art would have found it obvious to modify the invention described in the rejection of claim 15 above under the teachings of Winterbottom to connect the first semiconductor device to the second semiconductor device through embedded optical packaging. This could be accomplished using methods and materials known to the art, and would predictably result in die-to-die communication free of pin count limitations and edge-of-chip reach of electrical interconnects.
Claim(s) 17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 20230296854 A1) in view of Winzer (US 20230077979 A1), and further in view of Zhang (US 9202803 B2)
Regarding claim 17:
Li in view of Winzer teaches the optical device of claim 16.
Li does not teach the bridge die embedding as claimed. It teaches bridge die embedding in the in the build up layers instead of the core explicitly.
Zhang teaches a bridge die embedded in a cavity formed in a substrate layer, like the glass core layer of Li.
Zhang teaches a first bridge die (280, Figure 11) embedded within the glass core (sits in cavity 276, Figure 7 and 8).
Before the effective filing date of the claimed invention, one of ordinary skill in the art would have found it obvious to modify the invention described in the rejection of claim 16 above under the teachings of Zhang to embed the bridge die embedding within the glass core of the invention in claim 16 as described by Li and Winzer. This may be accomplished using methods known in the art (laser ablation for forming the cavity within which the embedding occurs) and materials and components (bridge die material) known in the art. Predictably, this would result in the accommodation of a thicker bridge die than a single build-up layer would allow, which reduces warpage and signal loss.
Regarding claim 19:
Li in view of Winzer teaches the optical device of claim 18.
Li further teaches bridge die embedding in the in the build up layers instead of the core explicitly (i.e. paragraph 19, the bridge circuitries as seen in Figure 1 may be used in the build up layers above glass core 504).
While Li does not expressly apply this to a third layer, this method of bridge die embedding would be obvious to use in the invention of claim 18 under the teachings of Li, as it allows the inventor to embed the bridge die in a component that is thicker and more resistant to warpage. This leads to fewer losses and greater mechanical rigidity.
Conclusion
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/PREET B PATEL/Examiner, Art Unit 2874
/THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874
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