DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/17/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 10-14 & 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Colleran et al. (US 7102438 B1, hereinafter, Colleran).
Regarding claim 1:
Colleran discloses in Figs. 4A & 20, and integrated circuit amplifier apparatus (Col. 4, lines 7-9, integrated circuits) comprising:
an operational amplifier (Fig. 20, operational amplifier gain element A) having a voltage input (Vin signal at Vin terminal) and an output (output terminal, Vout);
an input capacitor (capacitor Cin) coupled to the voltage input;
a feedback capacitor (capacitor CFB) coupled between the output and the voltage input; and a feedback field effect transistor “FET” (FET transistor as shown in Fig. 4A, which discloses CTD circuit 20, Col. 5, lines 8-10, field effect transistor having its source, drain and well shorted together) configured as a gate tunneling resistor in parallel with the feedback capacitor (capacitor CFB) between the output and the voltage input, the FET having a gate, a source, and a drain, wherein configuring the FET as a gate tunneling resistor (Col. 5, lines 25-29, tunneling junction and tunneling devices) includes coupling the source and drain together.
Regarding claim 2:
Colleran discloses in Figs. 4A & 20, further comprising:
a bias FET (element 162 of Fig. 20, and Fig. 4A, circuit 20 include transistor, see Col. 5, lines 59-60, Devices 64 and 66 may be matched or not, as desired) configured as a gate tunneling resistor, the bias FET connected between a bias voltage source (Vtun) and the feedback FET (160, transistor as discussed above).
Regarding claim 3:
Colleran discloses in Figs. 4A & 20, wherein gates of the feedback FET and the bias FET are coupled with each other (Figs. 4A & 20,note that “i” terminal of 162 connected to “i” terminal of 160, where “I” terminal equal gate terminal or control terminal.
Regarding claim 10:
Colleran discloses wherein the feedback FET is a metal oxide field effect transistor “MOSFET” (see Col. 5, source/drain regions of the FETs).
Regarding claims 11 & 20:
Colleran discloses in Figs. 4A & 20, an integrated circuit amplifier apparatus or a method comprising:
a fully differential operational amplifier (as shown in Fig. 20) having differential voltage inputs (Vin), a first differential output (Vout), and a complementary second differential output (Vout);
a first feedback capacitor (CFB, top) coupled from the first differential output to one of the inputs;
a first feedback field effect transistor (FET) (circuit 160 include transistor FET), as discussed in claim 1) configured as a gate tunneling resistor in parallel with the first feedback capacitor;
a second feedback capacitor (CFB, bottom) coupled from the second differential output to the other of the differential voltage inputs, the second feedback capacitor (CFB, bottom) having a same capacitance as the first feedback capacitor; and
a second feedback FET (164, similar as discussed circuit 160) configured as a gate tunneling resistor in parallel with the second feedback capacitor.
Regarding claim 12:
Colleran discloses in Figs. 4A & 20, wherein each FET (Fig. 4A, discloses circuit 20 includes FET, where drain and source connected together) has a gate, a source, and a drain, wherein configuring each FET as a gate tunneling resistor includes coupling the source and the drain within each FET together.
Regarding claim 13:
Colleran discloses in Figs. 4A & 20, further comprising: a first bias FET (circuit 162 of Fig. 20, wherein the circuit 20 include transistor FET as shown in Fig. 4A) configured as a gate tunneling resistor, the first bias FET coupled between a first bias voltage source (Vtun) and the first feedback FET (circuit 160).
Regarding claim 14:
Colleran discloses in Figs. 4A & 20, further comprising: a second bias FET (circuit 166 which includes FET as discussed above in Fig. 4A) configured as a gate tunneling resistor, the second bias FET coupled between the first bias voltage source and the second feedback FET (164, similar as discussed circuit 160, which includes transistor FET).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 4 & 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Colleran.
Regarding claim 4:
Colleran discloses in Figs. 4A & 20, wherein the feedback FET (160 of Fig. 20) is a first feedback FET except for a second feedback configured as a gate tunneling resistor in parallel with the feedback capacitor between the output and the voltage input.
However, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have added a second feedback configured as a gate tunneling resistor in parallel with the feedback capacitor between the output and the voltage input since it has been held that mere duplication of essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Regarding claims 8 & 9:
Colleran discloses the limitations as applied in claim 1 except for wherein the feedback FET (it is noted that Figs. 4A & 20 of Colleran which discloses the feedback which include FET transistor) has a thickness of gate oxide of about 0.8 nanometers (nm) to about 2.2 nm, wherein the thickness enables quantum tunneling current to flow through the gate oxide from a channel beneath the gate oxide; and (Claim9) wherein an equivalent resistance of the feedback FET configured as a gate tunneling resistor is greater than 1 giga-ohm (GΩ). It would have been obvious to one having ordinary skill in the art at the time the invention was made to wherein the feedback FET has a thickness of gate oxide of about 0.8 nanometers (nm) to about 2.2 nm, wherein the thickness enables quantum tunneling current to flow through the gate oxide from a channel beneath the gate oxide; and wherein an equivalent resistance of the feedback FET configured as a gate tunneling resistor is greater than 1 giga-ohm (GΩ), since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Claims 7 & 19 are rejected under 35 U.S.C. 103 as being unpatentable over Colleran in view of Taylor (US 7317351 B2).
Regarding claims 7 & 19:
Colleran discloses the limitations as applied in claim 1 except for an attenuator or feedback amplifier between the output and the feedback FET (note that the transistor which having drain and source connected together, i.e., capacitor).
Taylor discloses in Fig. 3, amplifier circuit comprising feedback circuit 312 which includes an amplifier 314.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the circuit of Colleran to have an amplifier, as taught by Taylor. Such a modification would have imparted the advantageous benefit of improving gain, stability and performance (Col. 3, lines 19-20), as taught by Taylor to Colleran reference, thereby suggesting the obviousness of such a modification.
Allowable Subject Matter
Claims 5-6 & 15-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 5 & 6 are allowable since the closest prior art (i.e. Colleran) does not disclose further comprising: a first bias FET configured as a gate tunneling resistor, the first bias FET connected between a first bias voltage source and the first feedback FET; a second bias FET configured as a gate tunneling resistor, the second bias FET connected between a second bias voltage source and the second feedback FET; and a plurality of pairs of double-throw switches, a switch of each pair connected with one of the bias FETs and another switch of the pair connected with one of the feedback FETs, the switches of each pair configured to mutually toggle.
Claims 15-18 are allowable since the closest prior art (i.e. Colleran) does not disclose further comprising: a third feedback FET configured as a gate tunneling resistor in parallel with the first feedback capacitor; a third bias FET configured as a gate tunneling resistor, the third bias FET coupled between a second bias voltage source and the third feedback FET; and a plurality of pairs of double-throw switches, a switch of each pair coupled with one of the bias FETs and another switch of the pair connected with one of the feedback FETs, the switches of each pair configured to mutually toggle.
Conclusion
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/KHIEM D NGUYEN/Examiner, Art Unit 2843
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