Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 – 8, 16, 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeong (US 20170251576).
Regarding claim 1, Jeong discloses an electronic device comprising:
a printed circuit board (a circuit substrate 110) including a conductive layer (a ground layer 117) and a conductive pad (the pads 141) connected to the conductive layer (117) and exposed to an outside of the printed circuit board (110);
an electric component (the component 120) disposed on a first region (the region containing the component 120) of the printed circuit board and the electric component electrically connected to the printed circuit board;
a conductive member (the wire loops 131-1 to 131-3) disposed on the conductive pad and the conductive member surrounding at least part of a periphery of the first region of the printed circuit board; and
a shielding member (the conductive layer 160) isolating the first region of the printed circuit board from the outside of the printed circuit board by covering the electric component (120) and the conductive member (131-1, 131-2), the shielding member electrically connected to the conductive layer (117).
Regarding claim 2, Jeong discloses the claimed invention as set forth in claim 1. Jeong further suggests another electric component (component 120’, Fig. 2) different from the electric component (the component 120 or 120’ include power amplifier, filters, transducer, wire bond dies, COMS circuits, integrated silicon-on-insulator circuit and the like; paragraph 22), the another electric component disposed on a second region (the region containing component 120’) of the printed circuit board spaced apart from the first region, wherein the shielding member isolates the first region and the second region from the outside of the printed circuit board by covering the first region and the second region (the conductive layer 160 covers both regions, Fig. 2), and wherein the conductive member (132-1) divides the first region from the second region by being disposed between the first region and the second region.
Regarding claim 3, Jeong discloses the claimed invention as set forth in claim 1. Jeong further discloses the conductive member (132-1) extends from the conductive pad (142), in a direction (the direction perpendicular to the surface of the substrate 110) in which one surface of the printed circuit board (110) on which the electric component (120) is disposed faces.
Regarding claim 4, Jeong discloses the claimed invention as set forth in claim 1. Jeong further suggests one end of the conductive member is in contact with the conductive pad (142), and wherein the other end of the conductive member opposite to the one end of the conductive member, and the other end of the conductive member is bent (131-1 is bent, Fig. 4) with respect to a direction in which one surface of the printed circuit board (110) faces.
Regarding claim 5, Jeong discloses the claimed invention as set forth in claim 1. Jeong further suggests one end of the conductive member (131-1, Fig. 4) is in contact with the conductive pad (141) and is bent (Fig. 4) with respect to a direction in which one surface of the printed circuit board (110) faces.
Regarding claim 6, Jeong discloses the claimed invention as set forth in claim 1. Jeong further suggests a summation of a height of the conductive member (131-1) and a height of the conductive pad (141) is smaller than a height of the electric component (120, Fig. 3B).
Regarding claim 7, Jeong discloses the claimed invention as set forth in claim 1. Jeong further suggests the conductive pad (140, Fig. 5A; 141, Fig. 5B; 141A,142A, 143A,144A, Fig. 5C) surrounds at least part of the periphery of the first region of the printed circuit board in which the electric component (120) is disposed, and the conductive pad is spaced apart from the electric component (Fig. 5C).
Regarding claim 8, Jeong discloses the claimed invention as set forth in claim 1. Jeong further discloses the conductive member includes a plurality of the conductive members surrounding the periphery of the first region of the printed circuit board by being spaced apart from each other (131, 132, 133, 134; Fig. 5A).
Regarding claim 16, Jeong discloses an electronic device comprising:
a printed circuit board (110, Fig. 1D) including one surface (top surface of 110), a side surface (side surface of 110) facing in a direction perpendicular to a direction in which the one surface faces, and a conductive layer (117) partially exposed through the side surface;
an electric component (120) electrically connected to the printed circuit board and the electric component disposed on the one surface (top surface) of the printed circuit board; and
a shielding member (160) isolating the one surface of the printed circuit board from an outside of the printed circuit board by covering the electric component and the side surface of the printed circuit board (160 cover the side surface of 110), and the shielding member electrically connected to the conductive layer (117).
Regarding claim 18, Jeong discloses the claimed invention as set forth in claim 16. Jeong further discloses a part of the conductive layer (117) exposed through the side surface of the printed circuit board (110, Fig. 1D) by being protrude from the side surface of the printed circuit board, and wherein the shielding member (160) covers the part of the conductive layer (117).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 9, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong (US 20170251576), in view of Higgins (US 5639989).
Regarding claim 9, Jeong discloses the claimed invention as set forth in claim 1.
Jeong does not explicitly disclose the shielding member includes: an adhesive layer in contact with the conductive member and the adhesive layer including a conductive material; and a non-conductive layer disposed on the adhesive layer.
Higgins teaches the shielding member (24, 60, 62, 64, Fig. 3; 72, 74, 76, Fig. 5) includes: an adhesive layer (solder 78; or layer 24) in contact with the conductive member (ground ring 56’ or 56) and the adhesive layer including a conductive material (74, 76); and a non-conductive layer (72) disposed on the adhesive layer.
It would have been obvious to one having skill in the art at the effective filing date of the invention to include conductive layer and non-conductive layer in the shielding layer in order to provide the electromagnetic shield property and protective layer for the electronic component.
Regarding claim 19, Jeong discloses the claimed invention as set forth in claim 16.
Jeong does not explicitly disclose the shielding member includes: an adhesive layer in contact with the side surface of the printed circuit board, and the adhesive layer including a conductive material; and a non-conductive layer disposed on the adhesive layer.
Higgins teaches the shielding member (24, 60, 62, 64, Fig. 3; 72, 74, 76, Fig. 5) includes: an adhesive layer (solder 78; or layer 24) in contact with the conductive member (ground ring 56’ or 56) and the adhesive layer including a conductive material (74, 76); and a non-conductive layer (72) disposed on the adhesive layer.
It would have been obvious to one having skill in the art at the effective filing date of the invention to include conductive layer and non-conductive layer in the shielding layer in order to provide the electromagnetic shield property and protective layer for the electronic component.
Allowable Subject Matter
Claims 10 – 15, 17, 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance:
Regarding claim 10, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claims 1 & 9, a combination of limitations that the shielding member further includes a shielding layer interposed between the adhesive layer and the non-conductive layer, the shielding layer being electrically connected to the conductive layer through the conductive material. None of the reference art of record discloses or renders obvious such a combination.
Regarding claim 11, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claims 1 & 9, a combination of limitations that the shielding member further includes a radiating layer interposed between the adhesive layer and the non-conductive layer. None of the reference art of record discloses or renders obvious such a combination.
Regarding claim 12, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claims 1 & 9, a combination of limitations that the shielding member further includes a separating layer interposed between the adhesive layer and the electric component, the separating layer electrically disconnecting the adhesive layer and the electric component. None of the reference art of record discloses or renders obvious such a combination.
Regarding claim 13, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 1, a combination of limitations that the conductive pad disposed on periphery of one surface of the printed circuit board, and wherein the conductive member extends from the conductive pad to a side surface of the printed circuit board along an outer surface of the printed circuit board. None of the reference art of record discloses or renders obvious such a combination.
Regarding claim 17, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 16, a combination of limitations that a conductive coating layer disposed on a part of the conductive layer exposed through the side surface of the printed circuit board, and wherein the shielding member covers the conductive coating layer. None of the reference art of record discloses or renders obvious such a combination.
Regarding claim 20, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claims 16 & 19, a combination of limitations that the shielding member further includes: a shielding layer interposed between the adhesive layer and the non-conductive layer, and the shielding layer electrically connected to the conductive layer, and a radiating layer interposed between the adhesive layer and the shielding layer. None of the reference art of record discloses or renders obvious such a combination.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Otsubo (US 12016112) discloses a substrate, a shield layer, a conductive member, and component, Fig. 4.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH B TRAN whose telephone number is (571)272-9289. The examiner can normally be reached M-F 8:00 AM - 6:00 PM.
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/BINH B TRAN/Primary Examiner, Art Unit 2848