DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 3 and 10-17 are objected to because of the following informalities:
Claim 3 recites “the number of the at least one deep trench ring unit” which should be replaced with “a number of the at least one deep trench ring unit” to avoid antecedent basis issue.
Claim 10 recites “with polysilicon material to,” (lines 18-19) which should be replaced with “with polysilicon material,” to improve claim language.
Claim 12 recites “the number of the at least one deep trench ring unit” which should be replaced with “a number of the at least one deep trench ring unit” to avoid antecedent basis issue.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-11, and 13-17 are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0212229 to Hu et al. (hereinafter Hu) in view of Liu (US 2023/0126794).
With respect to claim 1, Hu discloses a combination structure of semiconductor deep trench devices (e.g., deep trench isolation structure and deep trench capacitor structure) formed within a semiconductor substrate (Hu, Figs. 1-2, ¶0002, ¶0011-¶0050), comprising:
a deep trench insulator device (120) (Hu, Figs. 1-2, ¶0002, ¶0012-¶0015) surrounding a high-voltage area (e.g., the active area 110 including MOS or bipolar transistors 101) and electrically insulating the high-voltage area (110) from exterior of the deep trench insulator device, wherein the deep trench insulator device includes at least one deep trench ring unit (120), each of the at least one deep trench ring unit including:
a deep trench ring (e.g., first trench 121 for the isolation structure 120) (Hu, Figs. 1-2, ¶0015-¶0017) in the semiconductor substrate (102), wherein the deep trench ring (121) appears polygonal in a top view (Hu, Fig. 2);
a first dielectric sidewall layer (e.g., oxide layer 123) (Hu, Figs. 1-2, ¶0016, ¶0040) formed and completely covering a bottom and sidewalls inside the deep trench ring (121); and
a first polysilicon fill region (126) (Hu, Figs. 1-2, ¶0017, ¶0043-¶0044) formed and filling an internal space of the first dielectric sidewall layer (123) with polysilicon material (126); and
a deep trench capacitor device (130) (Hu, Figs. 1-2, ¶0018-¶0020) including a plurality of deep trench capacitor units (e.g., a row of the deep trench capacitors 130) and a conductive feature (e.g., metallization 160/162 to form a second capacitor electrode) (Hu, Figs. 1-2, ¶0028, ¶0048), wherein each of the deep trench capacitor units includes:
a deep trench hole (131) (Hu, Figs. 1-2, ¶0018-¶0020, ¶0034), in the semiconductor substrate (102), wherein the deep trench hole (131) appears circular in a top view (Hu, Fig. 2);
a second dielectric sidewall layer (133) (Hu, Figs. 1-2, ¶0020, ¶0040), and completely covering a bottom and sidewalls inside the deep trench hole (131);
a second polysilicon fill region (136) (Hu, Figs. 1-2, ¶0020, ¶0043-¶0044), filling an internal space of the second dielectric sidewall layer (133) with polysilicon material; and
a conductive feature (e.g., metallization 160/162 to form a first capacitor electrode) formed and connected to the second polysilicon fill region (136) (Hu, Figs. 1-2, ¶0028, ¶0048), serving as one of electrode contacts for the deep trench capacitor device (130);
wherein the conductive feature (e.g., metallization 160/162 in contact with doped region 132 to form a second capacitor electrode) (Hu, Figs. 1-2, ¶0028, ¶0048) is formed on the semiconductor substrate (102) outside the plural deep trench capacitor units (130), serving as an electrode contact for the deep trench capacitor device (130).
Further, Hu does not specifically disclose a deep trench capacitor device including a cathode; an anode, serving as one of positive electrode contacts for the deep trench capacitor device; wherein the cathode serving as a negative electrode contact for the deep trench capacitor device.
However, Liu teaches forming a semiconductor structure (Liu, Fig. 2F, ¶0005, ¶0029-¶0153) comprising a deep trench capacitor device including multiple trench capacitors, wherein the external electrode (113/1122/102) of the capacitor is formed by the doped region (102) and serves as a cathode (Liu, Fig. 2F, ¶0150), and the internal electrode (1121/1101) of each deep trench capacitor is formed by the conductive layer filled inside the deep trench hole, and serves as an anode, to provide different voltages to achieve an electric field between the internal and the external electrodes to form a decoupling capacitor with increased capacitance and stabilized voltage (Liu, Fig. 2F, ¶0084, ¶0150-¶0153).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combination structure of semiconductor deep trench devices of Hu by forming the external electrode of the deep trench capacitor as a cathode, and the internal electrode of the deep trench capacitor as an anode as taught by Liu to have the combination structure of semiconductor deep trench devices, comprising: a deep trench capacitor device including a cathode; an anode, serving as one of positive electrode contacts for the deep trench capacitor device; wherein the cathode serving as a negative electrode contact for the deep trench capacitor device, in order to provide different voltages to achieve an electric field between the internal and the external electrodes to form a decoupling capacitor with increased capacitance and stabilized voltage (Liu, ¶0084, ¶0150-¶0153).
Regarding limitations “a deep trench ring formed by a vertical etching process step etching the semiconductor substrate; a first dielectric sidewall layer by an oxidation growth process step; a first polysilicon fill region by a depositing process step; a deep trench hole formed by the same vertical etching process step as the deep trench ring, vertically etching the semiconductor substrate; a second dielectric sidewall layer formed by the same oxidation growth process step as the first dielectric sidewall layer; a second polysilicon fill region formed by the same deposition process step as the first polysilicon fill region”, the examiner submits that the language or phrase "formed by a vertical etching process step etching the semiconductor substrate…by an oxidation growth process step… by a depositing process step…by the same vertical etching process step as the deep trench ring, vertically etching the semiconductor substrate… by the same oxidation growth process step as the first dielectric sidewall layer… by the same deposition process step as the first polysilicon fill region" is directed towards the process of making a deep trench ring, a first dielectric sidewall layer, a first polysilicon fill region, the deep trench ring in a deep trench hole in the semiconductor substrate, a second dielectric sidewall layer, and a second polysilicon fill region. It is well settled that "product-by-process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language "formed by a vertical etching process step etching the semiconductor substrate…by an oxidation growth process step… by a depositing process step…by the same vertical etching process step as the deep trench ring, vertically etching the semiconductor substrate… by the same oxidation growth process step as the first dielectric sidewall layer… by the same deposition process step as the first polysilicon fill region " only requires a structure, a deep trench ring, a first dielectric sidewall layer, a first polysilicon fill region, the deep trench ring in a deep trench hole in the semiconductor substrate, a second dielectric sidewall layer, and a second polysilicon fill region, which does not distinguish the invention from Hu, who teaches the structure as claimed.
Regarding claim 2, Hu in view of Liu discloses the combination structure of semiconductor deep trench devices as claimed in claim 1. Further, Hu discloses the combination structure of semiconductor deep trench devices, wherein the plural deep trench capacitor units (130) are arranged in a face-centered cubic packing (Hu, Fig. 2, ¶0018-¶0020).
Regarding claim 4, Hu in view of Liu discloses the combination structure of semiconductor deep trench devices as claimed in claim 1. Further, Hu discloses the combination structure of semiconductor deep trench devices, wherein the deep trench capacitor device further includes a first N-type well region (129) (Hu, Figs. 1-2, ¶0020, ¶0028) formed in the semiconductor substrate (102), electrically connected to the cathode (e.g., the external electrode serving as a cathode, in view of Liu) and connected to an external surface of the second dielectric sidewall layer (133) of each of the plural deep trench capacitor units (130).
Regarding claim 5, Hu in view of Liu discloses the combination structure of semiconductor deep trench devices as claimed in claim 4. Further, Hu discloses the combination structure of semiconductor deep trench devices, wherein the deep trench capacitor device (130) further includes a first N-type buried region (e.g., NBL 104) (Hu, Figs. 1-2, ¶0020, ¶0028) formed below the first N-type well region (129) in the semiconductor substrate (102), electrically connected (e.g., through the N+ region 132) to the first N-type well region (129), and connected (e.g., through the N+ region 132) to an external surface of the second dielectric sidewall layer (133) of each of the plural deep trench capacitor units (130).
Regarding claim 6, Hu in view of Liu discloses the combination structure of semiconductor deep trench devices as claimed in claim 1. Further, Hu discloses the combination structure of semiconductor deep trench devices, wherein the deep trench capacitor unit (130) further includes a first shallow trench insulator region (118) (Hu, Figs. 1, 16, ¶0046) formed at the uppermost exterior of the deep trench hole (131).
Regarding claim 7, Hu in view of Liu discloses the combination structure of semiconductor deep trench devices as claimed in claim 1. Further, Hu discloses the combination structure of semiconductor deep trench devices, wherein the deep trench insulator device (120) further includes a second N-type well region (129) (Hu, Figs. 1, 17, ¶0017, ¶0047) formed in the semiconductor substrate (102), surrounding an exterior of the at least one deep trench ring unit (120).
Regarding claim 8, Hu in view of Liu discloses the combination structure of semiconductor deep trench devices as claimed in claim 7. Further, Hu discloses the combination structure of semiconductor deep trench devices, wherein the deep trench insulator device (120) further includes a second N-type buried region (NBL 104) (Hu, Figs. 1, 17, ¶0015-¶0017) formed below the second N-type well region (129) in the semiconductor substrate (120), surrounding the exterior of the at least one deep trench ring unit (120).
Regarding claim 9, Hu in view of Liu discloses the combination structure of semiconductor deep trench devices as claimed in claim 1. Further, Hu discloses the combination structure of semiconductor deep trench devices, wherein the deep trench ring unit (120) further includes two second shallow trench insulator regions (118) (Hu, Figs. 1, 16, ¶0014-¶0017, ¶0046), respectively formed at each uppermost exterior on both sides of the deep trench ring (120).
With respect to claim 10, Hu discloses a manufacturing method of a combination structure of semiconductor deep trench devices (e.g., forming deep trench isolation structure and deep trench capacitor structure) (Hu, Figs. 1-2, 4-18, ¶0002, ¶0011-¶0050), comprising:
simultaneously forming a deep trench ring (121) (Hu, Figs. 1-2, 6, ¶0015, ¶0018, ¶0034) and a deep trench hole (131) by vertically etching a semiconductor substrate (120) with a vertical etching process step (600), wherein the deep trench ring (121) appears polygonal and the deep trench hole (131) appears circular in a top view (Hu, Fig. 2);
simultaneously forming a first dielectric sidewall layer (123) (Hu, Figs. 1-2, 9, ¶0016, ¶0019, ¶0040) and a second dielectric sidewall layer (133) with an oxidation growth process step (900), wherein the first dielectric sidewall layer (123) is formed and completely covers the bottom and sidewalls inside the deep trench ring (131), and the second dielectric sidewall layer (133) is formed and completely covers the bottom and sidewalls inside the deep trench hole (131);
simultaneously forming a first polysilicon fill region (126) (Hu, Figs. 1-2, 12-13, ¶0017, ¶0020, ¶0043-¶0044) and a second polysilicon fill region (136) by a depositing process step (1200), wherein the depositing process step fills an internal space of the first dielectric sidewall layer (123) with polysilicon material to, and fills an internal space of the second dielectric sidewall layer (133) with polysilicon material; and
forming a conductive feature (e.g., metallization 160/162 to form a first capacitor electrode) and connecting it to the second polysilicon fill region (136) (Hu, Figs. 1-2, 18, ¶0028, ¶0048);
wherein the deep trench ring (121), the first dielectric sidewall layer (123), and the first polysilicon fill region (126) form a deep trench ring unit (120), wherein at least one of the deep trench ring unit constitutes a deep trench insulator device (120) (Hu, Figs. 1-2, ¶0015-¶0017);
wherein the deep trench insulator device (120) surrounds a high-voltage area (110) and electrically insulates the high-voltage area (e.g., the active area 110 including MOS or bipolar transistors 101) (Hu, Figs. 1-2, ¶0002, ¶0012-¶0015) from exterior of the deep trench insulator device (120);
wherein the deep trench hole (131) (Hu, Figs. 1-2, ¶0018-¶0020, ¶0028), the second dielectric sidewall layer (133), the second polysilicon fill region (136), and the conductive feature (e.g., metallization 160/162 to form a first capacitor electrode) form a deep trench capacitor unit (130, in a specific row), wherein a plurality of the deep trench capacitor units and a conductive feature (e.g., metallization 160/162 to form a second capacitor electrode) constitute a deep trench capacitor device (130);
wherein the conductive feature (e.g., metallization 160/162 in contact with doped region 132 to form a second capacitor electrode) (Hu, Figs. 1-2, ¶0028, ¶0048) is formed on the semiconductor substrate (1 02) outside the plural deep trench capacitor units (130), serving as a second electrode contact for the deep trench capacitor device (130).
Further, Hu does not specifically disclose forming an anode; the anode to form a deep trench capacitor unit; a cathode to constitute a deep trench capacitor device; wherein the anode serves as one of positive electrode contacts for the deep trench capacitor device; wherein the cathode is formed on the semiconductor substrate outside the plural deep trench capacitor units, serving as a negative electrode contact for the deep trench capacitor device.
However, Liu teaches forming a semiconductor structure (Liu, Fig. 2F, ¶0005, ¶0029-¶0153) comprising a deep trench capacitor device including multiple trench capacitors, wherein the external electrode (113/1122/102) of the capacitor is formed by the doped region (102) and serves as a cathode (Liu, Fig. 2F, ¶0150), and the internal electrode (1121/1101) of each deep trench capacitor is formed by the conductive layer filled inside the deep trench hole, and serves as an anode, to provide different voltages to achieve an electric field between the internal and the external electrodes to form a decoupling capacitor with increased capacitance and stabilized voltage (Liu, Fig. 2F, ¶0084, ¶0150-¶0153).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the manufacturing method of a combination structure of semiconductor deep trench devices of Hu by forming the external electrode of the deep trench capacitor as a cathode, and the internal electrode of the deep trench capacitor as an anode as taught by Liu to have the manufacturing method of a combination structure of semiconductor deep trench devices, comprising: forming an anode; the anode to form a deep trench capacitor unit; a cathode to constitute a deep trench capacitor device; wherein the anode serves as one of positive electrode contacts for the deep trench capacitor device; wherein the cathode is formed on the semiconductor substrate outside the plural deep trench capacitor units, serving as a negative electrode contact for the deep trench capacitor device, in order to provide different voltages to achieve an electric field between the internal and the external electrodes to form a decoupling capacitor with increased capacitance and stabilized voltage (Liu, ¶0084, ¶0150-¶0153).
Regarding claim 11, Hu in view of Liu discloses the manufacturing method of a combination structure of semiconductor deep trench devices as claimed in claim 10. Further, Hu discloses the manufacturing method of a combination structure of semiconductor deep trench devices, wherein the plural deep trench capacitor units (130) are arranged in a face-centered cubic packing (Hu, Fig. 2, ¶0018-¶0020).
Regarding claim 13, Hu in view of Liu discloses the manufacturing method of a combination structure of semiconductor deep trench devices as claimed in claim 10. Further, Hu discloses the manufacturing method of a combination structure of semiconductor deep trench devices, further comprising: simultaneously forming a first N-type well region (e.g., 129, in the deep trench capacitor region 130) and a second N-type well region (e.g., 129, in the deep trench isolation region 120) with a same process step (1700) (Hu, Figs. 1-2, 17, ¶0020, ¶0028, ¶0047-¶0048); wherein the first N-type well region (129) is formed in the semiconductor substrate (120), electrically connected to the cathode (e.g., the external second capacitor electrode), and connected to an external surface of the second dielectric sidewall layer of each of the plural deep trench capacitor units (131); wherein the second N-type well region is formed in the semiconductor substrate (102), surrounding exterior of the at least one deep trench ring unit (120)4
Regarding claim 14, Hu in view of Liu discloses the manufacturing method of a combination structure of semiconductor deep trench devices as claimed in claim 13. Further, Hu discloses the manufacturing method of a combination structure of semiconductor deep trench devices, further comprising: simultaneously forming a first N-type buried region (e.g., NBL 104 in the capacitor region 130) (Hu, Fig. 4, ¶0030-¶0031) and a second N-type buried region (e.g., NBL 104 in the isolation region 120) with a same process step; wherein the first N-type buried region is formed below the first N-type well region (129) in the semiconductor substrate (102), electrically connected (e.g., through the N+ region 132) to the first N-type well region (129), and connected to the external surface of the second dielectric sidewall layer (133) of each of the plural deep trench capacitor units (130); wherein the second N-type buried region is formed below the second N-type well region in the semiconductor substrate, surrounding the exterior of the at least one deep trench ring unit (120).
Regarding claim 15, Hu in view of Liu discloses the manufacturing method of a combination structure of semiconductor deep trench devices as claimed in claim 10. Further, Hu discloses the manufacturing method of a combination structure of semiconductor deep trench devices, further comprising: simultaneously forming a first shallow trench insulator region (118) (Hu, Fig. 16, ¶0046) and two second shallow trench insulator regions (118) with a same process step; wherein the first shallow trench insulator region is formed at uppermost exterior of the deep trench hole (131); wherein the two second shallow trench insulator regions are respectively formed at each uppermost exterior on both sides of the deep trench ring (121).
Regarding claim 16, Hu in view of Liu discloses the manufacturing method of a combination structure of semiconductor deep trench devices as claimed in claim 10. Further, Hu discloses the manufacturing method of a combination structure of semiconductor deep trench devices, further comprising: after forming the first polysilicon fill region (126) and the second polysilicon fill region (136), planarizing (Hu, Figs. 14-15, ¶0045) an upper surface of the semiconductor substrate by a chemical mechanical polishing process step (CMP process 1400).
Regarding claim 17, Hu in view of Liu discloses the manufacturing method of a combination structure of semiconductor deep trench devices as claimed in claim 10. Further, Hu discloses the manufacturing method of a combination structure of semiconductor deep trench devices, further comprising: after forming the first shallow trench insulator region (118) (Hu, Fig. 16, ¶0046) and the two second shallow trench insulator regions (118), planarizing an upper surface of the semiconductor substrate by a chemical mechanical polishing process step.
Claims 3 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0212229 to Hu in view of Liu (US 2023/0126794) as applied to claim 1 (claim 10), and further in view of Anderson et al. (US 2012/0153431, hereinafter Anderson).
Regarding claim 3, Hu in view of Liu discloses the combination structure of semiconductor deep trench devices as claimed in claim 1. Further, Hu does not specifically disclose the combination structure of semiconductor deep trench devices, wherein the number of the at least one deep trench ring unit is plural and the plural deep trench ring units appear as arranged in concentric multilayers in a top view.
However, Anderson teaches forming an integrated circuit (Anderson, Figs. 14-16, ¶0048- ¶0055, ¶0070-¶0079) comprising a deep trench capacitor (230) and a deep trench isolation structure (210) including plural deep trench rings (211a/211b) arranged in concentric multilayers in a top view, and surrounding N-well region (221) including a semiconductor device, to provide deep trench isolation structures with improved density and excellent isolation.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the combination structure of semiconductor deep trench devices of Hu/Liu by forming a deep trench isolation structure including plural deep trench rings as taught by Anderson to have the combination structure of semiconductor deep trench devices, wherein the number of the at least one deep trench ring unit is plural and the plural deep trench ring units appear as arranged in concentric multilayers in a top view, in order to provide deep trench isolation structures with improved density and excellent isolation (Anderson, ¶0048- ¶0055, ¶0070-¶0074).
Regarding claim 12, Hu in view of Liu discloses the manufacturing method of a combination structure of semiconductor deep trench devices as claimed in claim 10. Further, Hu does not specifically disclose the manufacturing method of a combination structure of semiconductor deep trench devices, wherein the number of the at least one deep trench ring unit is plural and the plural deep trench ring units appear as arranged in concentric multilayers in a top view.
However, Anderson teaches forming an integrated circuit (Anderson, Figs. 14-16, ¶0048- ¶0055, ¶0070-¶0079) comprising a deep trench capacitor (230) and a deep trench isolation structure (210) including plural deep trench rings (211a/211b) arranged in concentric multilayers in a top view, and surrounding N-well region (221) including a semiconductor device, to provide deep trench isolation structures with improved density and excellent isolation.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the manufacturing method of a combination structure of semiconductor deep trench devices of Hu/Liu by forming a deep trench isolation structure including plural deep trench rings as taught by Anderson to have the manufacturing method of a combination structure of semiconductor deep trench devices, wherein the number of the at least one deep trench ring unit is plural and the plural deep trench ring units appear as arranged in concentric multilayers in a top view, in order to provide deep trench isolation structures with improved density and excellent isolation (Anderson, ¶0048- ¶0055, ¶0070-¶0074).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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