DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election, without traverse, of species I encompassing claims 1-20 in the “Response to Election / Restriction Filed - 08/03/2026”, is acknowledged.
However, listing of all claims on species I is against the suggested guideline given in “Requirement for Restriction/Election – 06/04/2026” which copied over here as “Applicant is advised that a reply to this requirement must include an identification of the species that is elected consonant with this requirement, and a listing of all claims readable thereon, including any claims subsequently added. An argument that a claim is allowable or that all claims are generic is considered nonresponsive unless accompanied by an election”.
On the interest of the compact prosecution, this office action exclude claim 14-20, as it is found, there is a search and/or examination burden for the patentably distinct species- I-VII as set forth in “Requirement for Restriction/Election - 06/04/2026”.
Claims 1-20 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species. There is no support in the elected embodiment of species 1, embodiment 1 of Figures 1A-2B, 3 for these claim limitations: for examples:
Claim 14 (and its dependent claims) comprises: inter alia, “upper interlayer insulating layer covering the information storage structure in the cell array region and covering the upper insulating structure in the connection region; a lower contact plug
Claim 19 and (its dependent claims) comprises: inter alia, the upper structure including a landing pad and an upper insulating structure surrounding the landing pad; …wherein the second upper interconnection is on a same height as the landing pad is from the substrate; landing pad 81 read on embodiment 1b and identified in species III.
Therefore these features are found on unelected species II-VI, respectively.. As at least the following reasons apply: The species or groupings of patentably indistinct species have acquired a separate status in the art due to their recognized divergent subject matter as exemplified by the aforementioned mutually exclusive characteristics, while the species or groupings of patentably indistinct species require a different field of search (different search strategies or search queries, as evidenced by the above-defined distinctions between the species) (see MPEP § 808.02) and/or the prior art applicable to one species would not likely be applicable to another species; and/or the inventions are likely to raise different non-prior art issues under 35 U.S.C. 101 and/or 35 U.S.C. 112, first paragraph. Therefore, restriction for examination purposes as indicated is proper
The requirement is still deemed proper , and is therefore made FINAL, and thus the required provisional election (see MPEP § 818.03(b)) remaines an election without traverse.
In view of the above, this office action considers claims 1-20 pending for prosecution, of which, non-elected claims 14-20 are withdrawn, and elected claims 1-13 are examined on their merits.
Specification
The specification is objected because, at least in paragraph [0063], the Fig.2B is used to illustrate the peripheral contact plugs CPP contacting interconnections 30p, 40p, 50p, and 81p disposed on different layers are arranged in the connection region EA, instead it should be Fig 2a. Appropriate correction is required here or in any other part of disclosure such as specification, drawings and/or like.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (40; Fig 2b; [0068]) = (element 40; Figure No. 2b; Paragraph No. [0068]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The primary reference citation, in this case, Kohyama may not be preceded by the inventor tag, wherein the other reference citation. For example Shin, will carry inventor tag. These conventions are used throughout this document.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Kohyama, Yusuke (US 20010012223 A1) hereinafter referenced as Kohyama; in view of SHIN; Yoo-cheo et al. (US 20210175244 A1) hereinafter referenced as Shin
Regarding claim 1, Kohyama teaches a semiconductor device (semiconductor memory device; Figs 2A-2C, 4; [0065+]), comprising (see the entire document, figs 2A-2C along with other relevant figures, specifically, as cited below):
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Kohyama Figure 2B
a substrate (40; Fig 2B; [0068) including a cell array region (Cell Array Region, hereinafter CAR; Fig 2B; [0068]) and a connection region (Peripheral Circuit Region; hereinafter PCR);
a peripheral circuit layer (comprising {cell transistor, peripheral transistor} hereinafter PCL; Fig 2B; [0068]) disposed on the substrate (40), the peripheral circuit layer including a circuit element (cell/peripheral transistor);
a bit line (47 BL; Fig 2B; [0069]) disposed on the peripheral circuit layer (PCL) that is in the cell array region (CAR);
a first upper interconnection (48 horizontal portion that connects 43, hereinafter 48W with vertical interconnect, hereinafter 48C; Fig 2; [0033]) disposed on the connection region (PCR) of the substrate (40), wherein the first upper interconnection (48) is at a same height ([0072]: the metallic wiring layer 48 is formed at the same level as that of the bit line 47) as the bit line (47 BL) is
a bit line insulating layer (46; Fig 2B; [0069]) surrounding the bit line (BL 47) in the cell array region (CAR) and (surrounding the first upper interconnection (48W) in the connection region (PCR);
an upper structure (structure overlaying 50; Fig 2B) disposed on the bit line (BL 47) and the first upper interconnection (48W), the upper structure including an upper insulating structure (51/55);
an information storage structure (Storage Node comprising {52,53,54}; Fig 2B; [0071]) disposed on the upper structure that is in the cell array region (CAR); and
a plurality of lower contact plugs (59/57; plurality is construed from fig 2A, where multiple bit-line and transistor is displayed) electrically connected to the at least one lower interconnection layer (48W) through the bit line insulating layer (47B), the plurality of lower contact plugs (57/59) disposed in the connection region (PCR).
But, Kohyama is silent on at least one lower interconnection layer (LL1/LL2; Figs 2A-2B) disposed between the peripheral circuit layer (PCL) and the bit line (47 BL) and between the peripheral circuit layer (PCL) and the first upper interconnection (48W);
However, in the analogous art, Shin teaches a semiconductor device 1000 having a memory cell array region I, a first peripheral circuit region II, a second peripheral circuit region III ( Figs 1A-1C;[0037-0038]), wherein (1B; [0069-0072]) one lower interconnection layer (between substrate 110 and bit line 216) disposed between the peripheral circuit layer and the bit line (216) and between the peripheral circuit layer and the first upper interconnection (234 of 230)
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate the interconnection layer of Lin into Kohyama as one lower interconnection layer (comprising all layers substrate 110 and bit line/dummy bitline 216/234) disposed between the peripheral circuit layer (PCL) and the bit line (BL 47), since this incorporation, at least, provides an electrical connection function between the peripheral circuit gate structure 120 and the upper interconnection layer 236. (Shin [0075]), and improve performance.
Regarding claim 2, the combination of (Kohyama and Shin) as applied to the semiconductor device of claim 1, further teaches, wherein the plurality of lower contact plugs (59/57; plurality is construed from fig 2A, where multiple bit-line and transistor is displayed) pass through the upper insulating structure (51/55; Fig 2B).
Regarding claim 3, the combination of (Kohyama and Shin) as applied to the semiconductor device of claim 1, further teaches, comprising:
an upper interlayer insulating layer (55; Figs 2B-2C; [0072]) covering the information storage structure (Storage Node comprising {52,53,54}; Fig 2B; [0071]) in the cell array region (CAR; Fig 2B) and covering the upper insulating structure (51) in the connection region (PCR), wherein the plurality of lower contact plugs (57) pass through the upper interlayer insulating layer (55).
Regarding claim 4, the combination of (Kohyama and Shin) as applied to the semiconductor device of claim 1, further discloses, wherein
the at least one lower interconnection layer (Shin all layers between substrate 110 and bit line/dummy bit line 216/234) includes a first lower interconnection layer (160; [0050]) and a second lower interconnection layer (182/184; [0054]), the second lower interconnection layer disposed on the first lower interconnection layer,
the first lower interconnection layer (160) includes a plurality of first lower interconnections,
the second lower interconnection layer includes a plurality of second lower interconnections, and
the plurality of lower contact plugs include a first lower contact plug (162), the first lower contact plug passing through the second lower interconnection layer (164) and contacting one first lower interconnection (168)of the plurality of first lower interconnections.
Regarding claim 5, the combination of (Kohyama and Shin) as applied to the semiconductor device of claim 4, further teaches, wherein (Obvious from Shin Fig 1B and [0075]:provides an electrical connection function between the peripheral circuit gate structure 120 and the upper interconnection layer 236 ) at least one first lower interconnection of the plurality of first lower interconnections is electrically connected to at least one second lower interconnection of the plurality of second lower interconnections, and one or more first lower interconnections of the plurality of first lower interconnections are electrically connected to the first lower contact plug.
Regarding claim 6, the combination of (Kohyama and Shin) as applied to the semiconductor device of claim 4, further teaches, wherein the plurality of lower contact plugs include a second lower contact plug (Shin 184; 1B) contacting one second lower interconnection (178) of the plurality of second lower interconnections.
Regarding claim 7, the combination of (Kohyama and Shin) as applied to the semiconductor device of claim 6, further teaches, wherein (obvious from Shin Fig 1B [0122 ] a width of a bottom portion of the contact hole may decrease due to a slope of the sidewall of the contact hole) a width of an upper surface of the first lower contact plug is greater than a width of an upper surface of the second lower contact plug.
Regarding claim 8, the combination of (Kohyama and Shin) as applied to the semiconductor device of claim 6, further teaches, wherein (obvious from Shin Fig 1B) a width of an upper surface of the first lower contact plug is equal to a width of an upper surface of the second lower contact plug.
Regarding claim 9, the combination of (Kohyama and Shin) as applied to the semiconductor device of claim 8, further teaches, wherein a lower width of the first lower contact plug is smaller than a lower width of the second lower contact plug, the lower width of the first lower contact plug is a width of the first lower contact plug on an upper surface of the first lower interconnection, and the lower width of the second lower contact plug is a width of the second lower contact plug on an upper surface of the second lower interconnection (obvious from Shin Fig 1B [0122 ] a width of a bottom portion of the contact hole may decrease due to a slope of the sidewall of the contact hole).
Regarding claim 10, the combination of (Kohyama and Shin) as applied to the semiconductor device of claim 8, further teaches, wherein a depth at which the first lower contact plug extends into the first lower interconnection is less than a depth at which the second lower contact plug extends into the second lower interconnection (obvious from Shin Fig 1B [0122 ] a width of a bottom portion of the contact hole may decrease due to a slope of the sidewall of the contact hole).
Regarding claim 11, the combination of (Kohyama and Shin) as applied to the semiconductor device of claim 4, further teaches, comprising (obvious from Shin Fig 1B [0122 ] a width of a bottom portion of the contact hole may decrease due to a slope of the sidewall of the contact hole):
an insulating pattern disposed on the upper insulating structure (84), the insulating pattern (Shin Fig 1B) including a material different from a material of the upper insulating structure (),
wherein a slope of a side surface of the first lower contact plug in a portion in which the first lower contact plug overlaps the insulating pattern in a horizontal direction is different from a slope of a side surface of the first lower contact plug in a portion in which the first lower contact plug overlaps the upper insulating structure in the horizontal direction (obvious from Shin Fig 1B [0122 ] a width of a bottom portion of the contact hole may decrease due to a slope of the sidewall of the contact hole).
Regarding claim 12, the combination of (Kohyama and Shin) as applied to the semiconductor device of claim 4, further teaches, further comprising:
a lower etch stop layer (Shin 140; [0079]) disposed below the bit line insulating layer; and
an upper etch stop layer (Shin 210; [0067])) disposed on the upper structure,
wherein a slope of a side surface of the first lower contact plug changes in a portion overlapping the lower etch stop layer in a horizontal direction, and the slope of the side surface of the first lower contact plug changes in a portion overlapping the upper etch stop layer in the horizontal direction.
Regarding claim 13, the combination of (Kohyama and Shin) as applied to the semiconductor device of claim 4, further teaches, wherein
the second lower interconnection layer includes a first material layer and a second material layer, the second material layer including a material different from a material of the first material layer and covering a plurality of side surfaces of the plurality of second lower interconnections, and
a slope of a side surface of the first lower contact plug in a portion in which the first lower contact plug overlaps the first material layer in a horizontal direction is different from a slope of a side surface of the first lower contact plug in a portion in which the first lower contact plug overlaps the second material layer in the horizontal direction (obvious from Shin Fig 1B [0122 ] a width of a bottom portion of the contact hole may decrease due to a slope of the sidewall of the contact hole).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOAZZAM HOSSAIN whose telephone number is (571)270-7960. The examiner can normally be reached M-F: 8:30AM - 6:00 PM.
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/MOAZZAM HOSSAIN/Primary Examiner, Art Unit 2898
September 1, 2026
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