DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Preliminary amendment filed 17 August 2026 is acknowledged. Claims 14-20 have been canceled. Claims 21-27 have been added. Claims 1-13 and 21-27 are pending.
Election/Restrictions
Applicant’s election of group I, claims 1-13, in the reply filed on 17 August 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 14-20 would have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method, there being no allowable generic or linking claim. However, these claims were canceled in the election made without traverse in the reply filed on 17 August 2026.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE COMPRISING HARD MASK RING SURROUNDING TOP ELECTRODE VIA.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-11 and 21-27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsu et al. (US Patent Application Publication 2021/0351348, hereinafter Hsu ‘348).
With respect to claim 1, Hsu ‘348 teaches (FIG. 5) a semiconductor device as claimed, comprising:
a bottom electrode (112) ([0025]);
a top electrode (118) over the bottom electrode (112) ([0025]);
a data storage structure (116) disposed between the top electrode (118) and the bottom electrode (112) ([0025]);
a top electrode via (TEVA) (131 and 132) electrically coupling the top electrode (118) ([0024]); and
a hard mask pattern (120) disposed over the top electrode (118) and surrounding the TEVA (131 and 132) ([0025]).
With respect to claim 2, Hsu ‘348 teaches wherein the hard mask pattern (120) is completely overlapped with the top electrode (118) ([0025]).
With respect to claim 3, Hsu ‘348 teaches wherein a thickness (when selected from the lower range of 30 nm; [0024]) of the top electrode (118) is less than a thickness (when selected from the upper range of 50 nm; [0023]) of the data storage structure (116) ([0023-0024]).
With respect to claim 4, Hsu ‘348 teaches further comprising a sidewall spacer (122) extending along sidewalls of the bottom electrode (112), the data storage structure (116), the top electrode (118) and the hard mask pattern (120), wherein the sidewall spacer protrudes upward beyond a top surface of the top electrode ([0025]).
With respect to claim 5, Hsu ‘348 teaches wherein the hard mask pattern (120) is sandwiched between the sidewall spacer (122) and the TEVA (131 and 132) ([0025]).
With respect to claim 6, Hsu ‘348 teaches further comprising an etch stop layer (126) disposed on the sidewall spacer (122) and the hard mask pattern (120), wherein the hard mask pattern is sandwiched between the etch stop layer and the top electrode (118) ([0025]).
With respect to claim 7, Hsu ‘348 teaches further comprising a bottom electrode via (BEVA) (110) underlying the bottom electrode (112) and contacting a bottom surface of the bottom electrode ([0022]).
With respect to claim 8, Hsu ‘348 teaches wherein an angle between an outer side surface of the hard mask pattern (120) and a top surface of the top electrode (118) ranges from 70° to 90° (the angle appears to be about 80°) in a cross-sectional view cut through the hard mask pattern and the TEVA (131 and 132) ([0025]).
With respect to claim 9, Hsu ‘348 teaches (FIG. 5) a semiconductor device as claimed, comprising:
a memory cell (114) ([0026]);
a top electrode via (TEVA) (131 and 132) overlying and contacting a top surface of the memory cell (114) ([0024]);
a bottom electrode via (BEVA) (110) underlying and contacting a bottom surface of the memory cell (114) ([0022]); and
a hard mask ring (120; see FIG. 19) extending along a bottom portion of a sidewall of the TEVA (131 and 132) ([0025]).
With respect to claim 10, Hsu ‘348 teaches wherein the memory cell (114) comprises: a bottom electrode (112); a top electrode (118) over the bottom electrode; and a magnetic tunnel junction (MTJ) (116) between the top electrode and the bottom electrode, wherein the hard mask ring (120) contacting both a top surface of the top electrode and the sidewall of the TEVA (131 and 132) ([0023-0025]).
With respect to claim 11, Hsu ‘348 teaches further comprising: a sidewall spacer (122) contacting sidewalls of the memory cell (114) and an outer side surface of the hard mask ring (120); an etch stop layer (126) covering the sidewall spacer and the hard mask ring and contacting the sidewall of the TEVA (131 and 132); and a dielectric layer (136) covering the etch stop layer and contacting the sidewall of the TEVA ([0022, 0025]).
With respect to claim 21, Hsu ‘348 teaches (FIG. 5) a semiconductor device as claimed, comprising:
a bottom electrode (112) ([0025]);
a top electrode (118) over the bottom electrode (112) ([0025]);
a data storage structure (116) disposed between the top electrode (118) and the bottom electrode (112) ([0025]);
a conductive via (131 and 132) electrically coupling the top electrode (118) ([0024]); and
a hard mask pattern (120) covering a periphery portion of the top electrode (118) and surrounding the conductive via (131 and 132) ([0025]).
With respect to claim 22, Hsu ‘348 teaches wherein the hard mask pattern (120) and the top electrode layer (118) comprise different materials ([0017-0018]).
With respect to claim 23, Hsu ‘348 teaches wherein a thickness of the hard mask pattern (120) is smaller than a thickness of the conductive via (131 and 132) ([0024-0025]).
With respect to claim 24, Hsu ‘348 teaches further comprising an etch stop layer (126) over the hard mask pattern (120) and surrounding the conductive via (131 and 132) ([0025]).
With respect to claim 25, Hsu ‘348 teaches further comprising a sidewall spacer (122) along sidewalls of the hard mask pattern (120), the top electrode (118), the data storage structure (116) and the bottom electrode (112) ([0025]).
With respect to claim 26, Hsu ‘348 teaches further comprising a dielectric layer (136) surrounding the conductive via (131 and 132) and covering the etch stop layer (126) ([0022]).
With respect to claim 27, Hsu ‘348 teaches wherein the hard mask pattern (120) comprises silicon dioxide, silicon nitride, silicon carbide or a combination thereof ([0018]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu ‘348 as applied to claim 9 above, and further in view of Chen et al. (US Patent Application Publication 2020/0127053, hereinafter Chen ‘053).
With respect to claim 12, Hsu ‘348 teaches the device as described in claim 9 above, including the additional limitation further comprising a memory cell region (500), wherein the memory cell (114) is disposed in the memory cell region ([0025]).
Thus, Hsu ‘348 is shown to teach all the features of the claim with the exception of further comprising a logic region, wherein an interconnect structure is disposed in the logic region at the same level as the memory cell.
However, Chen ‘053 teaches (FIG. 17) a logic region (506), wherein an interconnect structure (118 and 120) is disposed in the logic region at the same level as a memory cell (102) ([0077]) to provide peripheral devices to implement read/write circuitry and/or other suitable circuitry for operation of memory cell structures ([0055]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor device of Hsu ‘348 further comprising a logic region, wherein an interconnect structure is disposed in the logic region at the same level as the memory cell as taught by Chen ‘053 to provide peripheral devices to implement read/write circuitry and/or other suitable circuitry for operation of memory cell structures.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu ‘348 and Chen ‘053 as applied to claim 12 above, and further in view of Tsai et al. (US Patent Application Publication 2004/0197986, hereinafter Tsai ‘986).
With respect to claim 13, Hsu ‘348 and Chen ‘053 teach the device as described in claim 12 above with the exception of the additional limitation further comprising a hard mask pattern surrounding the interconnect structure in the logic region.
However, Tsai ‘986 teaches (FIG. 2J) a hard mask pattern (224) surrounding an interconnect structure (240 and 250) in a logic region (203) to protect an underlying conductive layer (223) during semiconductor processing until time to make contact thereto ([0024, 0032-0033]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor device of Hsu ‘348 and Chen ‘053 further comprising a hard mask pattern surrounding the interconnect structure in the logic region as taught by Tsai ‘986 to protect an underlying conductive layer during semiconductor processing until time to make contact thereto.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Dang et al. (US Patent Application Publication 2016/0064664); You et al. (US Patent Application Publication 2016/0268499); and Yang et al. (US Patent Application Publication 2019/0074440) teach MRAM devices comprising a hard mask surrounding a top electrode via.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher M. Roland whose telephone number is (571)270-1271. The examiner can normally be reached Monday-Friday, 10:00AM-7:00PM Eastern.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at (571)270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.M.R./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
Prosecution Insights