DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
2. Claim 5 is objected to because of the following informalities: Claim 5 recites: “cleaning the e top surface” which should be changed to “cleaning the top surface” for readability.
Appropriate correction is required.
Double Patenting
3. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/forms/. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
4. Claims 1-5 and 7 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 9-11 and 13 of U.S. Patent No. 11,251,121 B2. Although the conflicting claims are not identical, they are not patentably distinct from each other because said claims of the present invention is a similar version or an obvious combination of elements of said claims of the above-identified U.S. Patent(s) with similar intended scope.
Specifically, the conflicting claims are listed below, and explanation is given where obviousness is not apparent:
Application Claims
Patent Claims
1. A method, comprising:
9. A method of fabricating a package structure, comprising:
forming an insulating encapsulant encapsulating a plurality of conductive posts;
providing at least one semiconductor die on a carrier, wherein the at least one semiconductor die comprises a plurality of conductive posts;
forming an insulating encapsulant encapsulating the at least one semiconductor die;
performing a planarization step to remove portions of the insulating encapsulant to reveal a top surface of the plurality of conductive posts; and
performing a planarization process by removing portions of the insulating encapsulant to reveal a top surface of the plurality of conductive posts;
cleaning the top surface of the plurality of conductive posts with a first solution to reduce a roughness of the top surface.
2. The method according to claim 1, wherein the top surface of the plurality of conductive posts with the first solution comprises cleaning the top surface with the first solution for 20 second to 80 seconds.
performing a single wafer spin cleaning process on the plurality of conductive posts after the planarization process, wherein the single wafer spin cleaning process comprises dropping a first solution onto the top surface of the plurality of conductive posts while spinning the carrier for 20 seconds to 80 seconds to clean the top surface of the plurality of conductive posts; and
forming a redistribution structure on the insulating encapsulant, wherein the steps of forming the redistribution structure comprises:
forming a plurality of conductive body portions, a plurality of first via portions and a plurality of dielectric layers alternately stacked, wherein the plurality of first via portions is formed with a lateral dimension that is kept constant from a first end to a second end of the plurality of first via portions, and a via cleaning process is performed on a surface of the second end after forming each of the plurality of first via portions, the via cleaning process comprises dropping the first solution onto the surface of the second end of the first via portions while spinning the carrier for 20 seconds to 80 seconds to clean the surface of the second end; and
debonding the carrier.
Note that patent claim 9 does not disclose “to reduce a roughness of the top surface” (in “cleaning the top surface of the plurality of conductive posts with a first solution to reduce a roughness of the top surface” in application claim 1). However, because the processes by which to clean the plurality of conductive posts are the same between application claim and patent claim (application claim: “the top surface of the plurality of conductive posts with the first solution comprises cleaning the top surface with the first solution for 20 second to 80 seconds”, patent claim: “dropping a first solution onto the top surface of the plurality of conductive posts while spinning the carrier for 20 seconds to 80 seconds to clean the top surface of the plurality of conductive posts”) and the cleaning solutions are the same (application claim 3, patent claims 10 and 11), one of ordinary skill in the art would expect patent claim 9 to imply and result in “to reduce a roughness of the top surface”, as presently claimed.
Application Claims
Patent Claims
3. The method according to claim 1, wherein the first solution comprises at least one acid selected from the group consisting of acetic acid, formic acid, citric acid, ascorbic acid, hydrofluoric acid, hydrochloric acid, phosphoric acid and nitric acid, or comprises at least one amine-based solution selected from the group consisting of ethanolamine, hydroxyethyl ethylenediamine, ammonium hydroxide and ammonium chloride.
10. The method of fabricating the package structure according to claim 9, wherein the first solution comprises at least one acid selected from the group consisting of acetic acid, formic acid, citric acid, ascorbic acid, hydrofluoric acid, hydrochloric acid, phosphoric acid and nitric acid.
11. The method of fabricating the package according to claim 9, wherein the first solution comprises an amine-based solution selected from the group consisting of ethanolamine, hydroxyethyl ethylenediamine, ammonium hydroxide and ammonium chloride.
4. The method according to claim 1, further comprising cleaning the top surface of the plurality of conductive posts with a second solution after cleaning the top surface with the first solution, wherein the second solution is different from the first solution.
13. The method of fabricating the package structure according to claim 9, wherein the single wafer spin cleaning process further comprises dropping a second solution onto the top surface of the plurality of conductive posts while spinning the carrier for 20 seconds to 80 seconds to clean the top surface of the plurality of conductive posts.
Although patent claim 13 does not disclose “wherein the second solution is different from the first solution”, patent claim recites “a second solution” which implies a solution different from the first solution; otherwise, patent claim 13 would have recited “the first solution” in place of “a second solution”.
As for claim 5 (5. The method according to claim 1, wherein after cleaning the top surface of the plurality of conductive posts with the first solution, the roughness of the top surface is in a range of 0.1 μm to 1 μm.), in a manner as detailed above for application claims 1 and 2, because the cleaning time (and the cleaning solution) are the same, one of ordinary skill in the art would expect a similar roughness range as presently claimed.
As for claim 7 (7. The method according to claim 1, further comprising: forming a planar seed layer on the top surface of the plurality of conductive posts; and forming first via portions on the planar seed layer, wherein the first via portions are electrically connected to the plurality of conductive posts.), the use of seed material for forming (electrically conductive) vias and other conductive structures is notoriously obvious in the semiconductor art, as evident in patent claim 20 (20. The method of fabricating the package structure according to claim 19, further comprising forming a planar seed layer on the first via portions after performing the via cleaning process, and wherein the conductive body portions are formed on the planar seed layer.)
Allowable Subject Matter
5. Claims 8-20 are allowable over the prior art of record.
Claim 6, in the absent of a terminal disclaimer, is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to teach or render obvious a method with all exclusive limitations as recited in claims 6, 8 and 15;
the method of claim 6 is characterized in that the plurality of conductive posts comprises a first metal layer, a second metal layer, a third metal layer and a solder layer, wherein the planarization step is performed to remove the solder layer and portions of the third metal layer to reveal a surface of the second metal layer, and wherein cleaning the top surface of the plurality of conductive posts with the first solution comprises cleaning the surface of the second metal layer with the first solution;
the method of claim 8 comprising providing conductive elements on a semiconductor wafer, wherein a top surface of the conductive elements is revealed from the semiconductor wafer, performing a single wafer spin cleaning process, and forming via portions disposed on and electrically connected to the conductive elements,
which may be characterized in that the performing a single wafer spin cleaning process comprises performing a single wafer spin cleaning process by dropping a first solution onto the top surface of the conductive elements while spinning the semiconductor wafer for at least 20 seconds;
and the method of claim 15 comprising forming a first redistribution layer on a carrier, comprising forming a plurality of conductive via portions, performing a cleaning step on the plurality of conductive via portions by cleaning a top surface of the plurality of conductive via portions with a first solution, forming a plurality of conductive body portions on the top surface of the plurality of conductive via portions, and repeating the formation of the plurality of conductive via portions and the formation of the plurality of conductive body portions so that the plurality of conductive via portions and the plurality of conductive body portions are alternately stacked to form the first redistribution layer,
which may be characterized in that the repeating the formation comprises the cleaning step.
Conclusion
6. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
(A) Tai et al. U.S. Patent 10,762,319 B2 discloses a manufacturing method of a fingerprint sensor, comprising providing a redistribution structure, forming a die and a plurality of conductive structures over the redistribution structure, wherein the die comprises a plurality of connection pads, encapsulating the die and the plurality of conductive structures by an encapsulant, and forming a first dielectric layer over the die, the encapsulant, and the plurality of conductive structures.
(B) Tsai et al. U.S. Patent 10,804,254 B2 discloses a method of forming a semiconductor structure, the method comprising forming a cavity substrate, wherein forming the cavity substrate comprises forming a masking layer on a substrate, patterning the masking layer to form pillar openings over the substrate, forming conductive pillars in respective ones of the pillar openings, patterning the masking layer to form a cavity opening over the substrate, and forming a cavity in the substrate below the cavity opening in the masking layer, placing a semiconductor device in the cavity, forming a molding compound along sidewalls of the semiconductor device, and forming a redistribution structure over the cavity substrate.
(C) Fujiwara et al. U.S. Patent 10,964,786 B2 discloses a polishing step for polishing a semi-insulating GaAs substrate, a rough cleaning step of roughly cleaning the polished semi-insulating GaAs substrate, and a precision cleaning step of precisely cleaning the roughly cleaned semi-insulating GaAs substrate.
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TU TU V HO whose telephone number is (571)272-1778. The examiner can normally be reached on Monday to Thursday 6:30 - 15:00, Monday through Thursday.
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04-19-2026
/TU-TU V HO/Primary Examiner, Art Unit 2818
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