DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The references cited in the IDS have been considered by examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: DISPLAY DEVICE HAVING A GATE CIRCUIT BETWEEN A PLURALITY OF DEMUX CIRCUIT.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nonaka et al (U.S. Patent Pub. No. 2019/0027090; already of record in IDS) in view of Kim (U.S. Patent Pub. No. 2007/0040764; already of record in IDS) and in view of Oh et al (U.S. Patent Pub. No. 2017/0115542).
Regarding claim 1, Nonaka discloses a display device (10), (fig. 1a, [0031]), comprising:
a substrate (102) including a display area (101) and a non-display area (i.e. peripheral area having circuit parts 107, 109 and 125) surrounding the display area, (fig. 1a, [0034-0035]);
a plurality of sub-pixels including a first sub-pixel (i.e. SPX1 located at the intersection of the first data line 105 output from data circuit block 191b and the scanning line 103 output from the scanning circuit block 171b) and a second sub-pixel (i.e. SPX2 located at the intersection of the second data line 105 output from data circuit block 191c and the scanning line 103 output from the scanning circuit block 171d) disposed on the display area (101) of the substrate (102), (see fig. 2a reproduced below for details, [0055-0058]);
a first sub-demux circuit (191b) connected to the first sub-pixel (SPX1) and disposed on the non-display area (i.e. peripheral area outside of display region 101) to transfer a first data output signal (i.e. data signal output to data line 105) to the first sub-pixel (SPX1), (see fig. 2a reproduced below and fig. 3, [0031, 0052, 0057 and 0074]);
a second sub-demux circuit (191c) connected to the second sub-pixel (SPX2) and disposed on the non-display area (i.e. peripheral area outside of display region 101) to transfer a second data output signal (i.e. data signal output to data line 105) to the second sub-pixel (SPX2), (see fig. 2a reproduced below and fig. 3, [0031, 0052, 0058 and 0074]);
a first data line (DL1) connecting the first sub-demux circuit (191b) and the first sub-pixel (SPX1), and extending in a first direction (vertical direction) in the display area (101), (see fig. 2a reproduced below, [0057]);
a second data line (DL2) connecting the second sub-demux circuit (191c), and the second sub-pixel (SPX2), and extending in the first direction (vertical direction) in the display area (101), (see fig. 2a reproduced below, [0058]);
a first connection line (106), (fig. 2a, [0057]);
a plurality of gate stages (171b and 171d) connected to the sub-pixels (SPX1 and SPX2), disposed on the non-display area (i.e. peripheral area of the display region 101) to transfer gate signals to the sub-pixels, (see fig. 2a reproduced below, [0034 and 0055 and 0057]), and including:
a first gate stage (171b) connected to the first sub-pixel (SPX1); and
a second gate stage (171d) connected to the second sub-pixel (SPX2) and disposed between the first sub-demux circuit (191b) and the second sub-demux circuit (191c), (see fig. 2a reproduced below);
a first gate line (GL1) connecting the first gate stage (171b) and the first sub-pixel (SPX1), extending in a horizontal direction in the display area (101), (see fig. 2 reproduced below, [0055]);
a second gate line (GL2) connecting the second stage (171d) and the second sub-pixel (SPX2), extending in the horizontal direction in the display area (101), (see fig. 2 reproduced below, [0057]);
wherein each of the first sub-demux circuit (191b) and the second sub-demux circuit (191c) selectively transfer (i.e. transfer data when the scanning signal selects scanning lines GL1 and GL2) the first data output signal (i.e. data signal output to data line DL1) and the second data output signal (i.e. data signal output to data line DL2) to the first sub-pixel (SPX1) and the second sub-pixel (SPX2), (see fig. 2 reproduced below, [0050-0051 and 0057-0058]), and
wherein the first sub-pixel (SPX1) is disposed in a first pixel row (i.e. row 1) and the second sub-pixel (SPX2) is disposed in a n-th pixel row (i.e. row 3) (where n is natural number of 3 or more), (see fig. 2a reproduced below).
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However, Nonaka does not mention a first connection line connected to the first sub-demux circuit and the second sub-demux circuit.
In a similar field of endeavor, Kim teaches:
a first connection line (i.e. line which outputs RGB digital video signals to data driver 300) connected to the first sub-demux circuit (570) and the second sub-demux circuit (560) and disposed on the non-display area (i.e. region above pixel portion 100) to transfer a first data input signal (i.e. signal output to line DL1) to the first sub-demux circuit (570) and transfer a second data input signal (i.e. signal output to line DL2) to the second sub-demux circuit (560), (fig. 3, [0040, 0045, 0049, 0057 and 0059]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Nonaka, by specifically providing the connection line to connect to first and second demultiplexers, as taught by Kim, for the purpose of outputting data signals to the demultiplexers.
However, Nonaka in view of Kim does not mention a first gate line connecting the first gate stage and the first sub-pixel, extending in the first direction in the display area.
In a similar field of endeavor, Oh teaches:
a first gate line (GL_1) connecting the first gate stage (GP_1) and the first sub-pixel (PX1), extending in the first direction (vertical direction DR1) in the display area (DA), and extending in a second direction (DR2) crossing the first direction (DR1) in the non-display area (NDA);
a second gate line (GL_2) connecting the second stage (GP_2) and the second sub-pixel (SPX2), extending in the first direction (DR1) in the display area (DA), and extending in a third direction (DR3) crossing the first direction (DR1) in the non-display area (NDA), (see fig. 2 reproduced below for details, [0051 and 0059-0065]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Nonaka in view of Kim, by specifically providing the first gate line connecting the first gate stage and the first sub-pixel, extending in the first direction in the display area, as taught by Oh, for the purpose of having the gate and data driving units desirably minimizing addition to the size of the display device, [0162].
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Regarding claim 2, Nonaka discloses wherein the sub-pixels further include a third sub-pixel and a fourth sub-pixel disposed on the display area of the substrate, further comprising:
a third sub-demux circuit (191d) connected to the third sub-pixel (SPX3) and disposed on the non-display area (i.e. peripheral area outside of display region 101) to transfer a third data output signal to the third sub-pixel (i.e. output of data line 105 to subpixel SPX3);
a fourth sub-demux circuit (191e) connected to the fourth sub-pixel (SPX4) and disposed on the non-display area (i.e. peripheral area outside of display region 101) to transfer a fourth data output signal to the fourth sub-pixel (i.e. output of data line 105 to subpixel SPX4), (see fig. 1b reproduced below for details and fig. 2a, [0036, 0039 and 0057-0058]); and
a second connection line (106), (fig. 2a, [0057]).
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However, Nonaka does not mention a second connection line.
In a similar field of endeavor, Kim teaches:
a second connection line (i.e. line which outputs RGB digital video signals to data driver 300) connected to the third sub-demux circuit (550) and the fourth sub-demux circuit (i.e. demultiplexer 540 which would be to the right side of demultiplexer 550) and dispose on the non-display area (i.e. region above pixel portion 100) to transfer a third data input signal (i.e. signal output to data line DL3) to the third sub-demux circuit (550) and transfer a fourth data input signal (i.e. signal output to data line DL4 which would be to the right side of DL3) to the fourth sub-demux circuit, (fig. 3, [0040, 0045, 0049 and 0061-0062]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Nonaka, by specifically providing the connection line to connect to first and second demultiplexers, as taught by Kim, for the purpose of outputting data signals to the demultiplexers.
Regarding claim 3, Nonaka discloses wherein a distance between the first sub-demux circuit (191b) and the second sub-demux circuit (191c) connected to the first connection line (106) is different from a distance between the third sub-demux circuit (191d) and the fourth sub-demux circuit (191e) connected to the second connection line (i.e. demultiplexers 191b and 191c are farther apart than demultiplexers 191d and 191e hence having different distance), (see figs. 1b and 2a reproduced above, [0055 and 0057]).
Regarding claim 4, Nonaka discloses wherein the distance between the first sub-demux circuit (191b) and the second sub-demux circuit (191c) connected to the first connection line (106) is larger than the distance between the third sub-demux circuit (191d) and the fourth sub-demux circuit (191e) connected to the second connection line (i.e. demultiplexers 191b and 191c are farther apart than demultiplexers 191d and 191e hence having a larger distance), (see figs. 1b and 2a reproduced above, [0055 and 0057]).
Regarding claim 5, Nonaka discloses wherein the gate stages further include:
a third gate stage (171f) connected to the third sub-pixel (SPX3) and disposed between the second sub-demux circuit (191c) and the third sub-demux circuit (191d); and
a fourth gate stage (171g) connected to the fourth sub-pixel (SPX4) and disposed between the third sub-demux circuit (191d) and the fourth sub-demux circuit (191e), (see fig. 1b reproduced above for details, [0036-0040]).
Regarding claim 6, Nonaka discloses wherein the number of the gate stages (i.e. two scanning circuit blocks 171) disposed between the first sub-demux circuit (191b) and the second sub-demux circuit (191c) is different from the number of the gate stages (i.e. one scanning circuit block 171g) disposed between the third sub-demux circuit (191d) and the fourth sub-demux circuit (191e), (see fig. 1b reproduced above, [0036-0040]).
Regarding claim 9, Nonaka discloses wherein the first sub-pixel (SPX1) is disposed in a first pixel column, and the second sub-pixel (SPX2) is disposed in a second pixel column, and the third sub-pixel (SPX3) is disposed in a third pixel column, and the fourth sub-pixel (SPX4) is disposed in a fourth pixel column, (see fig. 1b reproduced above, [0036-0040]).
Allowable Subject Matter
Claims 8-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Allowance
Claim 7, none of the prior art of record teaches alone or in combination the limitation “a plurality of light emitting stages connected to the sub-pixels and disposed on the non-display area to transfer light emitting signals to the sub-pixels, wherein the light emitting stages include: a first light emitting stage connected to the first sub-pixel; a second light emitting stage connected to the second sub-pixel and disposed between the first sub-demux circuit and the second sub-demux circuit; a third light emitting stage connected to the third sub-pixel and disposed between the second sub-demux circuit and the third sub-demux circuit; and a fourth light emitting stage connected to the fourth sub-pixel and disposed between the third sub-demux circuit and the fourth sub-demux circuit.”
Claim 8 is dependent upon claim 7 is allowed for the reason mentioned above in claim 7.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to LONG D PHAM whose telephone number is (571)270-5573. The examiner can normally be reached Monday - Friday: 9am-5pm EST.
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/LONG D PHAM/Primary Examiner, Art Unit 2623
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