DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/17/2024 and 10/28/202. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In Claim 8, line 2, the recitation of “the intermediate node” is unclear because the intermediate node does not appear clearly defined and also lack of antecedent basis. Further clarification is needed.
Claims 9-10 are rejected due to their dependency.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 & 14-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yanduru et al. (US 20120092074 A1), hereinafter Yanduru.
Regarding claim 1 & 16:
Yanduru discloses in Fig. 5 a Doherty power amplifier (see title and paragraph [0033], Doherty Power Amplifier) or a method comprising:
a first amplifier (511) with a first amplifier output (a node between element 513 and 511), wherein the first amplifier (511) is configured to produce an amplified first output signal, and the first amplifier output is characterized by a first amplifier output capacitance (FET transistor which has an intrinsic output capacitance provide by its parasitic drain-source capacitance and configure to produce an amplified first output signal at its drain, see well-known Doherty amplifier, reference 2014/0347133, Fig. 5, capacitance between drain and source);
a second amplifier (512) with a second amplifier output (a node between element 516 and 512), wherein the second amplifier (512)is configured to produce an amplified second output signal, and the second amplifier output is characterized by a second amplifier output capacitance (FET transistor which has an intrinsic output capacitance provide by its parasitic drain-source capacitance and configure to produce an amplified second output signal at its drain);
a reconfigurable impedance inverter circuit (elements 513-529) that includes a combining node (a node between element 528 and element 527) configured to combine the amplified first output signal with the amplified second output signal, wherein the combining node is characterized by a combining node impedance,
a first variable network (e.g. circuit forms by elements 513, 514 and 515) coupled to the first amplifier output, wherein the first variable network and, a second variable network (e.g. circuit forms by elements 519-527) coupled between the first amplifier output and the combining node, wherein the second variable network is configured to provide a series inductance (inductance 520, 524, 526 and 527) between the first amplifier output and the combining node, and a third variable network (circuit forms by elements 516-518) coupled to the second amplifier output and to the combining node; and
an output impedance transformer (form by element 528 and 529) coupled between the combining node and an output (a node, far right of element 528) of the Doherty power amplifier, wherein the output impedance transformer includes a fourth variable network configured to establish the combining node impedance except for the first amplifier output capacitance establish a first amplifier effective output capacitance that is less than the first amplifier output capacitance; and wherein the third variable network and the second amplifier output capacitance establish a second amplifier effective output capacitance that is less than the second amplifier output capacitance;
Yanduru discloses in paragraph 0035, to achieve the frequency tunable Doherty PA, at least one of a tunable element that allows a continuous range of tunable capacitance, or a switchable device that operates in either a capacitive or open state is used in the frequency tunable Doherty PA and in paragraph 0036, wherein a change in a RF capacitance, or in other words, capacitance tuning. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have set or characterized the first amplifier output capacitance establish a first amplifier effective output capacitance that is less than the first amplifier output capacitance; and wherein the third variable network and the second amplifier output capacitance establish a second amplifier effective output capacitance that is less than the second amplifier output capacitance since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 2:
Yanduru discloses wherein the first amplifier includes a first power transistor(transistor 511) with a first drain terminal and a first source terminal, wherein the first drain terminal corresponds to the first amplifier output; the first amplifier output capacitance is a first drain-source capacitance between the first drain terminal and the first source terminal (FET transistor which has an intrinsic output capacitance provide by its parasitic drain-source capacitance and configure to produce an amplified first output signal at its drain);
the second amplifier includes a second power transistor with a second drain terminal and a second source terminal, wherein the second drain terminal corresponds to the second amplifier output; and the second amplifier output capacitance is a second drain-source capacitance between the second drain terminal and the second source terminal (FET transistor which has an intrinsic output capacitance provide by its parasitic drain-source capacitance and configure to produce an amplified second output signal at its drain) and it is well-known in the art where a Field-Effect Transistor (FET) inherently has a parasitic capacitance between the drain and source, known as Cds (Drain-Source Capacitance).
Regarding claim 14:
Yanduru discloses further comprising: an amplifier controller (control logic circuit, see paragraph [0037], control logic circuit are incorporated into a monolithically integrated circuit in order to provide switchable devices and tunable capacitors) coupled to the first, second, third, and fourth variable networks, wherein, the amplifier controller (control logic) is capable of configured to receive a signal indicative of a full power state, and in response, to provide first control signals to the first, second, third, and fourth variable networks to establish the Doherty power amplifier into a first amplifier state in which the first amplifier effective output capacitance has a first capacitance value, the second amplifier effective output capacitance has a second capacitance value, the series inductance has a first inductance value, and the combining node impedance has a first impedance value, and the amplifier controller (control logic circuit) is capable of configured to receive a signal indicative of a first backoff power state, and in response, to provide second control signals to the first, second, third, and fourth variable networks to establish the Doherty power amplifier into a second amplifier state in which the first amplifier effective output capacitance has a third capacitance value that is less than the first capacitance value, the second amplifier effective output capacitance has a fourth capacitance value that is less than the second capacitance value, the series inductance has a second inductance value that is greater than the first inductance value, and the combining node impedance has a second impedance value that is greater than the first impedance value (control logic, see paragraph [0037], control logic are incorporated into a monolithically integrated circuit in order to provide switchable devices and tunable capacitors).
Regarding claim 15:
Yanduru discloses wherein: the first amplifier is a carrier amplifier (see paragraph [0046], first transistor 511, which is also referred to as a carrier transistor 511); and the second amplifier is a peaking amplifier (a second transistor 512, which is also referred to as the peaking transistor 512).
Regarding claim 17:
Yanduru discloses further comprising reconfiguring the Doherty power amplifier by: reconfiguring the first variable network (e.g. circuit forms by elements 513, 514 and 515 which tunable elements) to modify the first amplifier effective output capacitance; simultaneously with reconfiguring the first variable network, reconfiguring the second variable network (e.g. circuit forms by elements 519-527 which is tunable elements) to modify the series inductance between the first amplifier output and the combining node; simultaneously with reconfiguring the first variable network, reconfiguring the third variable network (includes tunable elements) to modify the second amplifier effective output capacitance; and simultaneously with reconfiguring the first variable network, reconfiguring the fourth variable network (includes tunable element) to modify the combining node impedance.
Regarding claim 18:
Yanduru discloses wherein: reconfiguring the first variable network (e.g. circuit forms by elements 513, 514 and 515 which tunable elements) to modify the first amplifier effective output capacitance includes providing, by an amplifier controller (control logic, see paragraph [0037], control logic are incorporated into a monolithically integrated circuit in order to provide switchable devices and tunable capacitors), first switch control signals to the first variable network that cause at least one first switching element in the first variable network to change states;
reconfiguring the second variable network to modify the series inductance between the first amplifier output and the combining node includes providing, by the amplifier controller, second switch control signals to the second variable network (e.g. circuit forms by elements 519-527 which is tunable elements) that cause at least one second switching element in the second variable network to change states; and reconfiguring the third variable network (includes tunable elements) to modify the second amplifier effective output capacitance includes providing, by the amplifier controller, third switch control signals to the third variable network that cause at least one third switching element in the third variable network to change states.
Regarding claim 19:
Yanduru discloses further comprising: receiving an amplifier state control signal (control logic circuit) that indicates at least one of a traffic loading condition, a power level (see paragraph 0034, power levels less than 2 watts), or an amplifier state; and determining, by the amplifier controller (control logic circuit), the first, second, and third switch control signals from a lookup table (e.g., control logic) that correlates values for the amplifier state control signal with states for the at least one first switching element, the at least one second switching element, and the at least one third switching element.
Regarding claim 20:
Yanduru discloses further comprising determining, by a base station controller (circuit of Yanduru may be used in base station, see paragraph [0007-0008], each of the RX and TX RF bands is approximately less than 80 MHz wide, however, the RX and TX RF bands are scattered across a frequency range of 698 MHz to 2680 MHz for base station RX bands that are used for uplink connections, and 728-2690 MHz for base station TX bands that are used for downlink connections. For example, within a frequency span of 365 MHz, there are four major RF bands defined in the LTE standard, including Digital Communication Service-1800 (DCS-1800), or band-3, Personal Communication Service (PCS1900), or band-2, Advanced Wireless Services (AWS), or band-4 and Universal Mobile Telecommunications Service 2100 (UMTS2100), or band-1.), a current traffic loading condition for a system in which the Doherty power amplifier is included; generating, by the base station controller, the amplifier state control signal based on the current traffic loading condition; and sending, by the base station controller, the amplifier state control signal to the amplifier controller.
Claim(s) 3-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yanduru in view of Liao et al. (US 20150130541 A1, of record, hereinafter Liao).
Regarding claim 3:
Yanduru discloses the limitations as applied in claim 1 except for a first reconfigurable shunt inductance network coupled between the first amplifier output and a ground reference node; and a second reconfigurable shunt inductance network coupled between the second amplifier output and the ground reference node.
Liao discloses in Figs. 3-4 & 8 a Doherty amplifier having a shunt inductor L1 being connected to a microstrip T1 and switch and wherein the shunt inductor connected in series between the microstrip T1 and ground.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have added shunt inductor and switch as taught by Liao. Such a modification would have imparted the advantageous benefit of optimizing efficiency within whole frequency band, see paragraph [0045), lines 15-16, as taught by Liao to Yanduru’s reference, thereby suggesting the obviousness of such a modification.
Regarding claim 4:
The combination (Yanduru and Liao) discloses wherein: the first variable network includes a number, M, of first reconfigurable shunt inductance legs, where M is an integer that is equal to or greater than 1, and a first shunt inductance leg of the first reconfigurable shunt inductance legs includes a first inductor (inductor L1, Fig. 8 of Liao) coupled in series with a first switching element (switch); and
the third variable network includes the number, M, of second reconfigurable shunt inductance legs, and a first shunt inductance leg of the second reconfigurable shunt inductance legs includes a second inductor (similarly, inductor L1, Fig. 8 of Liao) coupled in series with a second switching element (similarly switch, Fig. 8 of Liao).
Regarding claim 5:
The combination (Yanduru and Liao) discloses wherein: the first variable network also includes a second shunt inductance leg with a third inductor coupled in series with a third switching element (see Fig. 8, inductor Ln and switch); and the third variable network also includes a second shunt inductance leg with a fourth inductor coupled in series with a fourth switching element (see Fig. 8, inductor Ln and switch).
Allowable Subject Matter
Claims 6-7 & 11-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 6-7 are allowable since the closest prior art does not disclose about wherein the second variable network comprises: a first inductor coupled between the first amplifier output and the combining node; and a first reconfigurable parallel inductance leg coupled in parallel with the first inductor, wherein the first reconfigurable parallel inductance leg includes a second inductor and a first switching element coupled in series between the first amplifier output and the combining node.
Claims 11-12 are allowable since the closest prior art does not disclose about wherein the second variable network comprises: a first inductor coupled between the first amplifier output and the combining node; a second inductor coupled in series with the first inductor between the first amplifier output and the combining node; and a first bypass switch coupled across the second inductor.
Claim 13 allowable since the closest prior art does not disclose about wherein the fourth variable network comprises: a phase shift element with a first end coupled to the combining node, and a second end coupled to the output of the Doherty power amplifier; a first variable capacitance circuit coupled between the first end of the phase shift element and a ground reference node; and a second variable capacitance circuit coupled between the second end of the phase shift element and the ground reference node.
Claims 8-10 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph; and if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)270-3941. The examiner can normally be reached Mon-Fri 8:00 AM-5:00 PM EST.
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/KHIEM D NGUYEN/Examiner, Art Unit 2843
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