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Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
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Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 7-12, 14, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Son et al. (US20210082941A1) in view of Cho et al. (US20220115397A1).
Regarding claim 1, Son teaches in Fig. 3 {the orientation of Son’s drawings may be rotated as necessary to meet the orientations recited in claim 1} a semiconductor device comprising:
a first substrate structure (CS) {[0019]}; and
a second substrate structure (PS) connected to the first substrate structure (CS) and including a substrate (SUB), circuit elements (PTR) on a lower surface of the substrate (SUB) that faces the first substrate structure (CS) {[0023]},
wherein the first substrate structure (CS) comprises:
gate electrodes (EL) stacked and spaced apart from each other along a first direction (D3) that is perpendicular to the lower surface of the substrate (SUB) {[0032, 0049]};
a supporter layer (USL) on the gate electrodes (EL) {[0028]};
channel structures (VS) extending in the first direction (D3) and penetrating the gate electrodes (EL), the channel structures (VS) respectively including a channel layer (SP) and a channel pad (PAD) on a lower end {[0041, 0061]};
separation regions (SPS) extending in the first direction (D3) and in a second direction (D2) that is perpendicular to the first direction (D3), the separation regions (SPS) penetrating the gate electrodes (EL) and being spaced apart from each other along a third direction (D1) that is perpendicular to the first (D3) and second directions (D2) {Figs. 2, 3; [0050]}; and
wherein the separation regions (SPS) respectively include first regions (regions of HO2) spaced apart from each other along the second direction (D2) and a second region (region of TR) on side surfaces of the first regions (regions of HO2) and extending in the second direction (D2) {Figs. 2, 8, 14B, 17; [0050, 0077, 0087]},
wherein the first regions (regions of HO2) and the channel structures (VS) penetrate the supporter layer (USL) {Figs. 3, 17; [0077]}, and
wherein a portion of a lower surface of the supporter layer (USL) is in contact with the second region (region of TR) {Figs. 3, 9, 10}.
Son does not teach a second substrate structure including second bonding metal layers between the lower surface of the substrate and the first substrate structure, and first bonding metal layers connected to the second bonding metal layers.
In an analogous art, Cho teaches in Fig. 10 and paragraph [0085] a second substrate structure (PERI) including second bonding metal layers (PAD2) between a lower surface of a substrate (201) and a first substrate structure (CELL), and first bonding metal layers (PAD1) connected to the second bonding metal layers (PAD2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Son’s semiconductor device based on the teachings of Cho, to achieve the above-identified subject matter, so as to provide electrical circuit connection between circuit elements of the second substrate structure and the channel structures. Cho [0086]. Moreover, all the claimed elements (e.g., second substrate structure, bonding metal layers, substrate, first substrate structure) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Cho) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 7, Son as modified by Cho teaches the semiconductor device of claim 1, and Son further teaches wherein the channel structures (VS) respectively include a first end adjacent to the supporter layer (USL) and a second end opposite to the first end and having the channel pad (PAD) thereon {Fig. 3; [[0046]}.
Regarding claim 8, Son as modified by Cho teaches the semiconductor device of claim 1, and Son further teaches wherein the supporter layer (USL) comprises at least one of Si, SiGe, SiC, AlxOy, or a metal material {[0029, 0031]}.
Regarding claim 9, Son as modified by Cho teaches the semiconductor device of claim 1, and Son further teaches wherein the first substrate structure (CS) further comprises interlayer insulating layers (IL1) alternately stacked with the gate electrodes (EL), and the supporter layer (USL) comprises a material (e.g., Ge/SiGe) different from a material (SiO) of the interlayer insulating layers (IL1) {[0029, 0031, 0039]}.
Regarding claim 10, Son as modified by Cho teaches the semiconductor device of claim 1, and Son further teaches wherein the first substrate structure (CS) further comprises a source conductive layer (SSL and or LSL) on the supporter layer (USL) and in contact with the channel layer (SP) {Fig. 3; [0048]}.
Regarding claim 11, Son as modified by Cho teaches the semiconductor device of claim 10, and Son further teaches wherein the source conductive layer (SSL and or LSL) overlaps the second region (region of TR) [of the separation regions (SPS)] in the first direction (D3) {Fig. 3}.
Regarding claim 12, Son as modified by Cho teaches the semiconductor device of claim 1, and Son further teaches wherein the separation regions (SPS) have curved side surfaces facing the side surfaces of the first regions (regions of HO2) [of the separation regions (SPS)] in plan view {Fig. 14B; [0087]}.
Regarding claim 14, Son teaches in Fig. 3 {the orientation of Son’s drawings may be rotated as necessary to meet the orientations recited in claim 1} a semiconductor device comprising:
a first substrate structure (CS) {[0019]}; and
a second substrate structure (PS) connected to the first substrate structure (CS) and including a substrate (SUB), circuit elements (PTR) on one surface of the substrate (SUB) {[0023]},
wherein the first substrate structure (CS) comprises:
gate electrodes (EL) stacked and spaced apart from each other along a first direction (D3) that is perpendicular to the one surface of the substrate (SUB) {[0032, 0049]};
a supporter layer (USL) on the gate electrodes (EL) {[0028]};
channel structures (VS) penetrating the gate electrodes (EL), extending in the first direction (D3), and respectively including a channel layer (SP) {[0041, 0061]};
separation regions (SPS) extending in the first direction (D3) and in a second direction (D2) that is perpendicular to the first direction (D3), the separation regions (SPS) penetrating the gate electrodes (EL), and being spaced apart from each other along a third direction (D1) that is perpendicular to the first (D3) and second directions (D2) {Figs. 2, 8, 14B, 17; [0050, 0077, 0087]}; and
wherein the channel structures (VS) respectively penetrate at least a portion of the supporter layer (USL) along the first direction (D3) {Figs. 3, 17; [0077]}, and
wherein the supporter layer (USL) includes regions overlapping the separation regions (SPS) along the first direction (D3) {Fig. 3}.
Son does not teach a second substrate structure including second bonding metal layers on the circuit elements, and first bonding metal layers connected to the second bonding metal layers.
Cho teaches in Fig. 10 and paragraphs [0030, 0085] a second substrate structure (PERI) including second bonding metal layers (PAD2) on circuit elements (220), and first bonding metal layers (PAD1) connected to the second bonding metal layers (PAD2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Son’s semiconductor device based on the teachings of Cho, to achieve the above-identified subject matter, so as to provide electrical circuit connection between circuit elements of the second substrate structure and the channel structures. Cho [0086]. Moreover, all the claimed elements (e.g., second substrate structure, bonding metal layers, circuit elements) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Cho) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 18, Son as modified by Cho teaches the semiconductor device of claim 14, and Son further teaches wherein the first substrate structure (CS) further comprises interlayer insulating layers (IL1) alternately stacked with the gate electrodes (EL), and the supporter layer (USL) comprises a conductive material (n-type doped polysilicon) or an insulating material that is different from a material (SiO) of the interlayer insulating layers (IL1) {[0029, 0031, 0039]}.
Regarding claim 19, Son teaches in Fig. 3 a data storage system comprising:
a semiconductor storage device (device of Fig. 1) comprising a first substrate structure (CS) including channel structures (VS), a second substrate structure (PS) including circuit elements (PTR) {Figs. 1, 3; [0019, 0023]};
wherein the first substrate structure (CS) further comprises:
gate electrodes (EL) stacked and spaced apart from each other along a first direction (D3) {[0032, 0049]};
a supporter layer (USL) on the gate electrodes (EL) {[0028]};
channel structures (VS) penetrating the gate electrodes (EL), extending in the first direction (D3), and respectively including a channel layer (SP), a channel insulation layer (VP), and a channel pad (PAD) at end portions thereof {[0041, 0061, 0082]}; and
separation regions (SPS) extending in the first direction (D3) and a second direction (D2) that is perpendicular to the first direction (D3), the separation regions (SPS) penetrating the gate electrodes (EL) {Fig. 2; [0050, 0087]},
wherein the channel structures (VS) penetrate the supporter layer (USL) {Fig. 3}, and
wherein the supporter layer (USL) is spaced apart from the channel layer (SP) by the channel insulation layer (VP) {Fig. 3; [0042]}.
Son does not teach the first substrate structure including first bonding metal layers, the second substrate structure including second bonding metal layers connected to the first bonding metal layers along a bonding surface, and the first direction is perpendicular to the bonding surface.
Cho teaches in Fig. 10 and paragraph [0085] a first substrate structure (CELL) including first bonding metal layers (PAD1), the second substrate (PERI) structure including second bonding metal layers (PAD2) connected to the first bonding metal layers (PAD1) along a bonding surface (surface between CELL and PERI), and the first direction (vertical, Z) is perpendicular to the bonding surface (surface between CELL and PERI). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Son’s semiconductor device based on the teachings of Cho, to achieve the above-identified subject matter, so as to provide electrical circuit connection between circuit elements of the second substrate structure and the channel structures. Cho [0086]. Moreover, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Cho) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Son does not teach the semiconductor storage device comprising an input/output pad electrically connected to the circuit elements, and a controller configured to be electrically connected to the semiconductor storage device through the input/output pad, and configured to control the semiconductor storage device.
Cho teaches in Fig. 13 and paragraphs [0137, 0142] a semiconductor storage device (1100) comprising an input/output pad (1101) electrically connected to circuit elements (1110), and a controller (1200) configured to be electrically connected to the semiconductor storage device (1100) through the input/output pad (1101), and configured to control the semiconductor storage device (1100). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Son’s semiconductor device as modified by Cho based on the further teachings of Cho, to achieve the above-identified subject matter, so as to that [w]hen a control command [for storing or retrieving data] is received from the external host through the host interface …, the processor … may control the semiconductor device … in response to the control command. Moreover, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Cho) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Son does not expressly teach the channel insulation layer is a dielectric layer.
Cho teaches in Fig. 10 and paragraph [0057] a channel insulation layer (145) is a dielectric layer. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Son’s semiconductor device as modified by Cho based on the further teachings of Cho, to achieve the above-identified subject matter, because [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Moreover, all the claimed elements (e.g., channel insulation layer, dielectric layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Cho) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Regarding claim 20, Son as modified by Cho teaches the data storage system of claim 19, and Son further teaches wherein the supporter layer (USL) includes a region crossing the separation regions (SPS) along a third direction (D1), which is perpendicular to the first (D3) and second directions (D2), on each of the separation regions (SPS) {Figs. 2, 3}.
Claim(s) 2-6 and 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Son in view of Cho as applied to claim 1 (for claims 2-6) and claim 14 (for claims 15-17) above, and further in view of Hong et al. (US20230042792A1).
Regarding claim 2, Son as modified by Cho teaches the semiconductor device of claim 1, but Son does not teach wherein inner side surfaces of the supporter layer are directly on the side surfaces of the first regions.
In an analogous art, Hong teaches in Figs. 6A and 6F and paragraph [0079] inner side surfaces of a supporter layer (SP) are directly on side surfaces of first regions (portion of SS1 Penetrating SP) [of the separation regions (SS1)]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Son’s semiconductor device as modified by Cho based on the teachings of Hong, to achieve the above-identified subject matter, so the support layer provides increased stability for the separation region by providing structural support for the separation region along three orthogonal axes. Moreover, all the claimed elements (e.g., inner side surfaces, supporter layer, side surfaces, first regions) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Hong) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 3, Son as modified by Cho teaches the semiconductor device of claim 1, but Son does not teach wherein the supporter layer includes a region overlapping with the second region in the first direction.
Hong teaches in Figs. 6A and 6F and paragraph [0079] a supporter layer (SP) includes a region overlapping with a second region (portion of SS1 resting on upper surface of SP) [of the separation regions (SS1)] in the first direction (vertical). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Son’s semiconductor device as modified by Cho based on the teachings of Hong, to achieve the above-identified subject matter, so the support layer provides increased stability for the separation region by providing structural support for the separation region along three orthogonal axes. Moreover, all the claimed elements (e.g., supporter layer, second region of separation regions) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Hong) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 4, Son as modified by Cho teaches the semiconductor device of claim 1, but Son does not teach wherein the second region does not penetrate the supporter layer.
Hong teaches in Figs. 6A and 6F and paragraph [0079] a second region (portion of SS1 resting on upper surface of SP) [of the separation regions (SS1)] does not penetrate the supporter layer (SP). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Son’s semiconductor device as modified by Cho based on the teachings of Hong, to achieve the above-identified subject matter, so the support layer provides increased stability for the separation region by providing structural support for the separation region along three orthogonal axes. Moreover, all the claimed elements (e.g., supporter layer, second region of separation regions) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Hong) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 5, Son as modified by Cho teaches the semiconductor device of claim 1, but Son does not teach wherein upper ends of the channel structures and upper ends of the separation regions are coplanar with or extend beyond an upper surface of the supporter layer.
Hong teaches in Figs. 6A and 6F and paragraph [0079] upper ends of channel structures (VS) and upper ends of separation regions (SS1) are coplanar with or extend beyond an upper surface of the supporter layer (SP) {the orientation of Hong’s drawings may be rotated to match the claimed orientation}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Son’s semiconductor device as modified by Cho based on the teachings of Hong, to achieve the above-identified subject matter, so the support layer provides increased stability for the separation region and channel structures by providing structural support for each along two or three orthogonal axes. Moreover, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Hong) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 6, Son as modified by Cho teaches the semiconductor device of claim 1, but Son does not teach wherein uppermost surfaces of the separation regions are coplanar with an upper surface of the supporter layer.
Hong teaches in Figs. 6A and 6F and paragraph [0079] uppermost surfaces of the separation regions (SS1) are coplanar with an upper surface of the supporter layer (SP) {the orientation of Hong’s drawings may be rotated to match the claimed orientation}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Son’s semiconductor device as modified by Cho based on the teachings of Hong, to achieve the above-identified subject matter, so the support layer provides increased stability for the separation region and channel structures by providing structural support for each along two or three orthogonal axes. Moreover, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Hong) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 15, Son as modified by Cho teaches the semiconductor device of claim 14, but Son does not teach wherein a first portion of each of the separation regions extends completely through the supporter layer in the first direction.
Hong teaches in Figs. 6A and 6F and paragraph [0079] a first portion of each of separation regions (SS1) extends completely through the supporter layer (SP) in the first direction (vertical). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Son’s semiconductor device as modified by Cho based on the teachings of Hong, to achieve the above-identified subject matter, so the support layer provides increased stability for the separation region by providing structural support for the separation region along three orthogonal axes. Moreover, all the claimed elements (e.g., separation regions, supporter layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Hong) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 16, Son as modified by Cho teaches the semiconductor device of claim 15, but Son does not teach wherein a second portion of each of the separation regions is in contact with one surface of the supporter layer.
Hong teaches in Figs. 6A and 6F and paragraph [0079] a second portion (portion resting on upper surface of SP) of each of the separation regions (SS1) is in contact with one surface of the supporter layer (SP). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Son’s semiconductor device as modified by Cho based on the teachings of Hong, to achieve the above-identified subject matter, so the support layer provides increased stability for the separation region by providing structural support for the separation region along three orthogonal axes. Moreover, all the claimed elements (e.g., separation regions, supporter layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Hong) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 17, Son as modified by Cho teaches the semiconductor device of claim 14, and Son further teaches wherein the separation regions (SPS) respectively include first regions (regions of HO2) spaced apart from each other along the second direction (D2), and a second region (region of TR) on side surfaces of the first regions (regions of HO2) and extending in the second direction (D2).
Son does not teach the first regions extend completely through the supporter layer.
Hong teaches in Figs. 6A and 6F and paragraph [0079] first regions (regions of SS1 penetrating SP) [of the separation regions (SS1)] extend completely through the supporter layer (SP). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Son’s semiconductor device as modified by Cho based on the teachings of Hong, to achieve the above-identified subject matter, so the support layer provides increased stability for the separation region by providing structural support for the separation region along three orthogonal axes. Moreover, all the claimed elements (e.g., first regions, separation regions, supporter layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Hong) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Son in view of Cho as applied to claim 1 above, and further in view of Kashima (US20200286910A1).
Regarding claim 13, Son as modified by Cho teaches the semiconductor device of claim 1, but Son does not teach wherein the first substrate structure further comprises string channel structures penetrating a lowest gate electrode among the gate electrodes and respectively connected to the channel structures.
In an analogous art Kashima teaches in Fig. 4 and paragraphs [0061, 0068] a first substrate structure (structure of Fig. 4) further comprises string channel structures (MP:UP) penetrating a lowest gate electrode (24) among the gate electrodes (22-24) and respectively connected to the channel structures (MP:LP) {the orientation of Kashima’s Fig. 4 may be rotated to achieve the claimed orientation}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Son’s semiconductor device as modified by Cho based on the teachings of Hong, to achieve the above-identified subject matter, because all the claimed elements (e.g., substrate structure, string channel structures, gate electrode, channel structures) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Hong) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al. (US20220384467A1) teaches an integrated circuit device includes a substrate, a peripheral wiring circuit that includes a bypass via and is disposed on the substrate, a peripheral circuit that includes an interlayer insulating layer surrounding at least a portion of the peripheral wiring circuit, and a memory cell array disposed on and overlapping the peripheral circuit. The memory cell array includes a base substrate, a plurality of gate lines disposed on the base substrate, and a plurality of channels penetrating the plurality of gate lines. The integrated circuit device further includes a barrier layer interposed between the peripheral circuit and the memory cell array. The barrier layer includes a bypass hole penetrating from a top surface to a lower surface of the barrier layer. The bypass via is disposed in the bypass hole.
Conclusion
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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