DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I, in the reply filed on 09/09/2026 is acknowledged. The traversal is on the ground(s) that search and examination of the entire application can be made without serious burden. This is found persuasive and therefore all claims are considered for examination.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: the term “internal sidewall of the interlayer insulating layer”, found in claim 19, or similar terminology clearly referring to the same feature is not present in the specification, making it unclear which sidewall(s) of the interlayer insulating layer is/are considered the “internal sidewall”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim(s) 1-20, the claim feature or are dependent upon claims which feature the limitation “on both sides of the gate structure” (emphasis added). The use of “both”, by its plain meaning, implies the existence of exactly two sides. However, since the gate structure is a three-dimensional structure and presumably does not extend infinitely in any direction and does not appear to form a closed loop, as disclosed, it must have more than two side surfaces. For example, in addition to the two side surfaces of the gate structure seen in a cross-sectional view perpendicular to the y-axis, such as shown in FIG. 2, there are two side surfaces in a cross-sectional view perpendicular to the x-axis. Additionally, “sides” may include a top or bottom surface or inside and outside. Alternatively, “sides of the gate structure” may refer to a positional relationship with the gate structure rather than a physical feature of the gate structure itself, i.e. being to the left/right of the gate structure from a certain perspective. Therefore, the meaning of the term “side” is indefinite in this context, and it is further indefinite which sides of the gate structure are considered “both” or, if there are only two sides of the gate structure, the geometry of the gate structure is unclear. For the purpose of examination, the examiner interprets “both” in “both sides of the gate structure” as meaning at least two, and “sides” as referring to a positional relationship rather than a physical feature of the gate structure.
Regarding claim(s) 1-13 and 18-20, the claim feature or are dependent upon claims which feature the limitation “on both side surfaces of the gate structure” (emphasis added). The use of “both”, by its plain meaning, implies the existence of exactly two side surfaces. However, since the gate structure is a three-dimensional structure and presumably does not extend infinitely in any direction which does not appear to form a closed loop, as disclosed, it must have more than two side surfaces. For example, in addition to the two side surfaces of the gate structure seen in a cross-sectional view perpendicular to the y-axis, such as shown in FIG. 2, there are two side surfaces in a cross-sectional view perpendicular to the x-axis. Therefore, it is indefinite which side surfaces of the gate structure are considered “both” or, if there are only two side surfaces of the gate structure, the geometry of the gate structure is unclear. For the purpose of examination, the examiner interprets “both” in “both side surfaces of the gate structure” as meaning at least two.
Further regarding claim(s) 7, the claim feature or are dependent upon claims which feature the limitation “on both side surfaces of the gate capping layer” (emphasis added). The use of “both”, by its plain meaning, implies the existence of exactly two side surfaces. However, since the gate capping layer is a three-dimensional structure and presumably does not extend infinitely in any direction and does not appear to form a closed loop, as disclosed, it must have more than two side surfaces. For example, in addition to the two side surfaces of the gate capping layer seen in a cross-sectional view perpendicular to the y-axis, such as shown in FIG. 2, there are two side surfaces in a cross-sectional view perpendicular to the x-axis. Therefore, it is indefinite which side surfaces of the gate capping layer are considered “both” or, if there are only two side surfaces of the gate capping layer, the geometry of the gate capping layer is unclear. For the purpose of examination, the examiner interprets “both” in “both side surfaces of the gate capping layer” as meaning at least two.
Regarding claim(s) 14-17, the claim feature or are dependent upon claims which feature the limitation “on both side surfaces of the gate electrode” (emphasis added). The use of “both”, by its plain meaning, implies the existence of exactly two side surfaces. However, since the gate electrode is a three-dimensional structure and presumably does not extend infinitely in any direction and does not appear to form a closed loop, as disclosed, it must have more than two side surfaces. For example, in addition to the two side surfaces of the gate electrode seen in a cross-sectional view perpendicular to the y-axis, such as shown in FIG. 2, there are two side surfaces in a cross-sectional view perpendicular to the x-axis. Therefore, it is indefinite which side surfaces of the gate electrode are considered “both” or, if there are only two side surfaces of the gate electrode, the geometry of the gate electrode is unclear. For the purpose of examination, the examiner interprets “both” in “both side surfaces of the gate electrode” as meaning at least two.
Further regarding claim(s) 14-17, the claim feature or are dependent upon claims which feature the limitation “on both side surfaces of the gate capping layer” (emphasis added). The use of “both”, by its plain meaning, implies the existence of exactly two side surfaces. However, since the gate capping layer is a three-dimensional structure and presumably does not extend infinitely in any direction and does not appear to form a closed loop, as disclosed, it must have more than two side surfaces. For example, in addition to the two side surfaces of the gate capping layer seen in a cross-sectional view perpendicular to the y-axis, such as shown in FIG. 2, there are two side surfaces in a cross-sectional view perpendicular to the x-axis. Therefore, it is indefinite which side surfaces of the gate capping layer are considered “both” or, if there are only two side surfaces of the gate capping layer, the geometry of the gate capping layer is unclear. For the purpose of examination, the examiner interprets “both” in “both side surfaces of the gate capping layer” as meaning at least two.
Regarding claim(s) 15, the claim feature or are dependent upon claims which feature the limitation “the both side surfaces of the gate structure” (emphasis added). There is insufficient antecedent basis for this limitation in the claim. Additionally, the use of “both”, by its plain meaning, implies the existence of exactly two side surfaces. However, since the gate structure is a three-dimensional structure and presumably does not extend infinitely in any direction which does not appear to form a closed loop, as disclosed, it must have more than two side surfaces. For example, in addition to the two side surfaces of the gate structure seen in a cross-sectional view perpendicular to the y-axis, such as shown in FIG. 2, there are two side surfaces in a cross-sectional view perpendicular to the x-axis. Therefore, it is indefinite which side surfaces of the gate structure are considered “both” or, if there are only two side surfaces of the gate structure, the geometry of the gate structure is unclear. For the purpose of examination, the examiner interprets “both” in “both side surfaces of the gate structure” as meaning at least two.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6-9, and 14-17 are rejected under 35 U.S.C. 102 (a)(1) and/or 102 (a)(2) as being anticipated by Chen et al. (US 20230369468 A1, hereinafter C1).
Regarding independent claim 1, C1 discloses in C1 FIG. 23A-B and 23H and associated text A semiconductor device, comprising:
a substrate (substrate 110);
an active pattern extending on the substrate in a first direction (base portions 112 on 110 extending in the x-direction);
a plurality of channel layers stacked on the active pattern, the plurality of channel layers being spaced apart from each other in a direction perpendicular to an upper surface of the substrate (semiconductor layers 124 are channel layers stacked on 112 and spaced apart in the z-direction, which is perpendicular to the upper surface of 110);
a gate structure crossing the active pattern (gate structures 240 cross 112), the gate structure surrounding the plurality of channel layers and extending in a second direction that intersects the first direction (240 surround 124 and extend in the y-direction, which intersects the x-direction);
blocking insulating layers on both side surfaces of the gate structure, respectively (CESL 230 is on at least two sides of 240), each of the blocking insulating layers having an upper region having a first thickness and a lower region having a second thickness smaller than the first thickness (as seen in annotated C1 FIG. 23H);
Ann FIG
source/drain patterns on portions of the active pattern on both sides of the gate structure (source/drain epitaxial structures 220, which are on portions of 112, are on at least two sides of 240), the source/drain patterns connecting side surfaces of the plurality of channel layers (side surfaces of 124 are connected by 220), and the source/drain patterns defining trenches therein, respectively (220 each have a trench, which is the region below the top surfaces of 220 filled by conductive layers 290);
contact structures on the source/drain patterns between the blocking insulating layers, the contact structures filling the trenches (conductive layers 290 are on 220, between 230, and fill the trenches); and
a metal-semiconductor compound layer between the source/drain patterns and the contact structures (metal alloy layers 280, which may include metal-semiconductor compounds as their material (C1 [0054]), are between 220 and 290).
Regarding dependent claim 2, C1 discloses in C1 FIG. 23A-B and 23H and associated text The semiconductor device of claim 1, wherein the lower region of each of the blocking insulating layers has a portion having a width decreasing along the direction perpendicular to the upper surface of the substrate (a lower portion of 230 tapers, decreasing in width along the negative z-direction).
Regarding dependent claim 3, C1 discloses in C1 FIG. 23A-B and 23H and associated text The semiconductor device of claim 1, wherein the lower region of each of the blocking insulating layers does not cover a region adjacent to lower ends of the both side surfaces of the gate structure (the lower region of 230 does not cover portions of 240, e.g., portions of 233 below the topmost surfaces of 124).
Regarding dependent claim 6, C1 discloses in C1 FIG. 23A-B and 23H and associated text The semiconductor device of claim 1, wherein the gate structure includes:
a gate electrode crossing the active pattern (240 includes work function metal layer 244 crossing 112), the gate electrode extending in the second direction and surrounding the plurality of channel layers (244 surrounds 124 and extends in the y-direction, which intersects the x-direction);
a gate insulating layer between the gate electrode and the plurality of channel layers (gate dielectric layer 242 is between 244 and 124);
gate spacers on both side surfaces of the gate electrode in the second direction, respectively (gate spacers 190 are on side surfaces of 244); and
a gate capping layer on the gate electrode and the gate spacers (dielectric caps 260 are on 244 and 190), the gate capping layer having a material different from a material of the gate spacers (190 may be silicon oxide (C1 [0035]), for example, while materials of 260 do not include silicon oxide (C1 [0051]));
Regarding dependent claim 7, C1 discloses in C1 FIG. 23A-B and 23H and associated text The semiconductor device of claim 6, wherein the upper region of each of the blocking insulating layers is on both side surfaces of the gate capping layer (the upper region of 230 is on at least two side surfaces of 260), and the lower region of each of the blocking insulating layers is on side surfaces of the gate spacers (the lower region of 230 is on side surfaces of 190).
Regarding dependent claim 8, C1 discloses in C1 FIG. 23A-B and 23H and associated text The semiconductor device of claim 6,
wherein the gate capping layer includes silicon nitride (SiN) (260 may be SiN (C1 [0051])), and
wherein the gate spacers include at least one of silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boronitride (SiBN), silicon oxyboronitride (SiOBN), and silicon oxycarbide (SiOC) (190 may be, for example, SiO2 (C1 [0035])).
Regarding dependent claim 9, C1 discloses in C1 FIG. 23A-B and 23H and associated text The semiconductor device of claim 8, wherein the blocking insulating layers include silicon nitride (SiN) (230 includes silicon nitride (C1 [0042])).
Regarding independent claim 14, C1 discloses in C1 FIG. 23A-B and 23H and associated text A semiconductor device, comprising:
a substrate (substrate 110);
an active pattern extending on the substrate in a first direction (base portions 112 on 110 extending in the x-direction);
a plurality of channel layers stacked on the active pattern, the plurality of channel layers being spaced apart from each other in a direction perpendicular to an upper surface of the substrate (semiconductor layers 124 are channel layers stacked on 112 and spaced apart in the z-direction, which is perpendicular to the upper surface of 110);
a gate structure (gate structures 240) including
a gate electrode crossing the active pattern (240 includes work function metal layer 244 crossing 112), the gate structure surrounding the plurality of channel layers and extending in a second direction that intersects the first direction (240 surrounds 124 and extends in the y-direction, which intersects the x-direction);
gate spacers on both side surfaces of the gate electrode, respectively (gate spacers 190 are on at least two side surfaces of 244), and
a gate capping layer on the gate electrode and the gate spacers (dielectric caps 260 are on 244 and 190), the gate capping layer having a material different from a material of the gate spacers (190 may be silicon oxide (C1 [0035]), for example, while materials of 260 do not include silicon oxide (C1 [0051]));
source/drain patterns along side surfaces of the plurality of channel layers (source/drain epitaxial structures 220 are on sides of 124), the source/drain patterns being on portions of the active pattern on both sides of the gate structure (220, which are on portions of 112, are on at least two sides of 240), and the source/drain patterns defining trenches therein, respectively (220 each have a trench, which is the region below the top surfaces of 220 filled by conductive layers 290);
blocking insulating layers including first portions on both side surfaces of the gate capping layer, respectively (portions of CESL 230 are on at least two sides of 260), and second portions extending from the first portions to side surfaces of the gate spacers, respectively (portions of 230 extending from the first portions, as interpreted, extend to side surfaces of 190), and each of the second portions having a thickness smaller than a thickness of each of the first portions (lower ends of 230 taper, having a thickness smaller than that of the first portion, as interpreted); and
contact structures on the source/drain patterns between the blocking insulating layers, the contact structures filling the trenches (conductive layers 290 are on 220, between 230, and fill the trenches).
Regarding dependent claim 15, C1 discloses in C1 FIG. 23A-B and 23H and associated text The semiconductor device of claim 14, wherein each of the second portions has a portion having a width decreasing along the direction perpendicular to the upper surface of the substrate (a lower portion of 230 tapers, decreasing in width along the negative z-direction), and each of the second portions does not cover a region adjacent to a lower end of each of the both side surfaces of the gate structure (the lower region of 230 does not cover portions of 240, e.g., portions of 233 below the topmost surfaces of 124).
Regarding dependent claim 16, C1 further discloses the semiconductor device of claim 14, wherein the gate capping layer and the blocking insulating layers include silicon nitride (SiN) (260 and 230 may be SiN (C1 [0051] and [0042], respectively)).
Regarding dependent claim 17, C1 further discloses the semiconductor device of claim 16, wherein the gate spacers include at least one of silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boronitride (SiBN), silicon oxyboronitride (SiOBN), and silicon oxycarbide (SiOC) (190 may be, for example, silicon oxide (C1 [0035])).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over C1, and further in view of Hudson et al. (US 20160163557 A1, hereinafter H1).
Regarding dependent claim 4, C1 discloses the semiconductor device of claim 1. C1 does not explicitly disclose the second thickness of the lower region of each of the blocking insulating layers is 5 nm or less.
However, in the same field of endeavor, H1 discloses the second thickness of the lower region of each of the blocking insulating layers is 5 nm or less (a protective layer analogous to C1’s 230 in that it is used to protect adjacent features during an etching process has a thickness between 3-5 nm (H1 [0091])).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to apply the protective layer dimensions of H1 to a thickness of the lower region of C1’s CESL 230 to provide a functional semiconductor device, since the dimensions of C1’s 230 are not otherwise disclosed.
Regarding dependent claim 5, C1 discloses the semiconductor device of claim 1. C1 does not explicitly disclose the first thickness of the upper region of each of the blocking insulating layers is in a range of 5 to 15 nm.
However, in the same field of endeavor, H1 discloses the first thickness of the upper region of each of the blocking insulating layers is in a range of 5 to 15 nm (a protective layer analogous to C1’s 230 in that it is used to protect adjacent features during an etching process has a thickness between 1-10 nm (H1 [0091])).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to apply the protective layer dimensions of H1 to a thickness of the upper region of C1’s CESL 230 to provide a functional semiconductor device, since the dimensions of C1’s 230 are not otherwise disclosed.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over C1, and further in view of Lilak et al. (US 11239236 B2, hereinafter L1).
Regarding dependent claim 10, C1 discloses the semiconductor device of claim 1. C1 does not explicitly disclose the trenches have a portion overlapping a lowest channel layer among the plurality of channel layers in a direction horizontal to the upper surface of the substrate.
However, in the same field of endeavor, L1 discloses in L1 FIG. 5D and associated text the trenches have a portion overlapping a lowest channel layer among the plurality of channel layers in a direction horizontal to the upper surface of the substrate (the trench corresponding to interconnect 516 overlaps the lowest of semiconductor channels 506 in the direction horizontal to substrate 501 in L1 FIG. 5D).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the deeper source/drain contact trench of L1 for the source/drain contact trench of C1 since the deeper trench is disclosed as a known alternative to the trench shown in L1 FIG. 5B, which extends to a depth within the source/drain region 505 of second transistor 520B which is comparable to that of the trench in source/drain features 220 of C1, and produces the same result of providing an electrical connection to source/drain features at either depth (L1 (59)-(64)).
Claims 11-13 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20230369468 A1, hereinafter C1), and further in view of Shih et al. (US 20240120381 A1, hereinafter S1).
Regarding dependent claim 11, C1 discloses the semiconductor device of claim 1. C1 does not explicitly disclose a first epitaxial layer along the side surfaces of the plurality of channel layers on a portion of a region of the active pattern on the both sides of the gate structure, and a second epitaxial layer on the first epitaxial layer, wherein the trenches are formed in the second epitaxial layer.
However, in the same field of endeavor, S1 discloses in S1 FIG. 7 and associated text a first epitaxial layer along the side surfaces of the plurality of channel layers on a portion of a region of the active pattern on the both sides of the gate structure (outer regions 711 of source/drain features 70 are along side surfaces of channel features 421 on sides of gate portions 43), and a second epitaxial layer on the first epitaxial layer (central region 712 of 70 is on 711).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the multi-layered source/drain features of S1 with the semiconductor device of C1 to provide tensile stress to channel features with improved lattice matching between outer regions and channels by having a multi-layered source/drain structure with differing concentrations of dopants (C1 [0008], [0039]). When combined, the resulting structure would be such that the trenches are formed in the second epitaxial layer, since the trenches of C1 are centered on source/drain features and S1’s second epitaxial layer corresponds to central regions of the source/drain features.
Regarding dependent claim 12, C1, as modified by S1, further discloses in S1 FIG. 7 and associated text The semiconductor device of claim 11, wherein each of the first epitaxial layer and the second epitaxial layer includes silicon germanium (SiGe) (70 (including 711 and 712) is an alloy of semiconductor elements, Si, and stressor elements, Ge (S1 [0035]), thus SiGe), and a first concentration of germanium (Ge) of the first epitaxial layer is lower than a second concentration of germanium (Ge) of the second epitaxial layer (“the first stressor elements in the central region 712 have an atomic concentration greater than that of the first stressor elements in each of the outer regions 711” (S1 [0039])).
Regarding dependent claim 13, C1, as modified by S1, further discloses in S1 FIG. 7 and associated text The semiconductor device of claim 12, wherein the first concentration is 5 atomic% to 20 atomic%, and the second concentration is 30 atomic% to 70 atomic% (711 has an atomic concentration of stressors of about 10%-30%, while 712 has an atomic concentration of stressors of about 30%-80% (S1 [0039])).
Regarding independent claim 18, C1 discloses in C1 FIG. 23A-B and 23H and associated text A semiconductor device, comprising:
a substrate (substrate 110);
an active pattern extending on the substrate in a first direction (base portions 112 on 110 extending in the x-direction);
a device isolation layer on the substrate and defining the active pattern (isolation structures 140 on 110 define 112);
a plurality of channel layers stacked on the active pattern, the plurality of channel layers being spaced apart from each other in a direction perpendicular to an upper surface of the substrate (semiconductor layers 124 are channel layers stacked on 112 and spaced apart in the z-direction, which is perpendicular to the upper surface of 110);
a gate structure crossing the active pattern (gate structures 240 cross 112), the gate structure surrounding the plurality of channel layers and extending in a second direction that intersects the first direction (240 surround 124 and extend in the y-direction, which intersects the x-direction);
blocking insulating layers on both side surfaces of the gate structure, respectively (CESL 230 is on at least two sides of 240), and each of the blocking insulating layers having an upper region having a first thickness and a lower region having a second thickness smaller than the first thickness (as seen in annotated C1 FIG. 23H);
source/drain patterns along side surfaces of the plurality of channel layers on portions of the active pattern on both sides of the gate structure (source/drain epitaxial structures 220, which are on portions of 112, are on side surfaces of 124 and at least two sides of 240);
an interlayer insulating layer on the device isolation layer and on the source/drain patterns (contact spacers 270 are on 140 and 220); and
contact structures penetrating the interlayer insulating layer (conductive layers 290 penetrate 270), the contact structures connected to the source/drain patterns, respectively, and the contact structures being between the blocking insulating layers (290 each connect to respective ones of 220 and are between 230).
C1 does not explicitly disclose the source/drain patterns including a first epitaxial layer, and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer defining a trench therein.
However, in the same field of endeavor, S1 discloses in S1 FIG. 7 and associated text the source/drain patterns including a first epitaxial layer (outer regions 711 of source/drain features 70), and a second epitaxial layer on the first epitaxial layer (central region 712 of 70 is on 711).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the multi-layered source/drain features of S1 with the semiconductor device of C1 to provide tensile stress to channel features with improved lattice matching between outer regions and channels by having a multi-layered source/drain structure with differing concentrations of dopants (C1 [0008], [0039]). When combined, the resulting structure would be such that the second epitaxial layer defining a trench therein, since the trenches of C1 are centered on source/drain features and S1’s second epitaxial layer corresponds to central regions of the source/drain features.
Regarding dependent claim 19, C1, as modified by S1, further discloses in C1 FIG. 23A-B and 23H and associated text The semiconductor device of claim 18, wherein each of the blocking insulating layers are not on an internal sidewall of the interlayer insulating layer through which the contact structures penetrate (230 is not on the sidewalls of 270 that face toward 290, which are considered internal sidewalls).
Regarding dependent claim 20, C1, as modified by S1, further discloses in C1 FIG. 23A-B and 23H and associated text The semiconductor device of claim 18, wherein each of the blocking insulating layers are not between bottom surfaces of the contact structures and the device isolation layer (230 is not between bottom surfaces of 290 and 140).
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
US 20200220018 A1, pertaining to multi-layer epitaxial layers with different doping concentrations and contact trenches.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVERETT TRAJAN RIRIE whose telephone number is (571) 272-9559. The examiner can normally be reached Mon - Thu 8:30 am - 6:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EVERETT T RIRIE/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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