DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement(s)
The Information Disclosure Statement(s) filed on May 17, 2024 was considered by the Examiner.
Election/Restrictions
Applicant's election with traverse of Species A and Sub-species c3 including claims 1-3, 5, 7-13, and 15-20 in the reply filed on June 30, 2026 is acknowledged. Claim 6 was not elected by Applicant and further, Examiner confirms that claim 6 is not directed to the elected Species and Sub-species. As claims 7-10 depend from claim 6, claims 7-10 are not directed to the elected Species and Sub-species. Accordingly, claims 7-10 are withdrawn from consideration.
Additionally, the above traversal is on the ground(s) that there must be a search burden for examination to be proper. This is not found persuasive because there is a search burden as specific keyword searches would need to be conducted to search for the mutually exclusive features of the different species such as the different gate electrode structures (either the gate electrodes become wider or narrower in a direction toward the substrate), the presence or omission of barrier layers (either a barrier layer is present between conductive layer ULC1 and the contact plug UCP1 or the barrier layer is not present between conductive layer ULC1 and the contact plug UCP1), the different distance relationships (either the distance D1 is the same or different as the distance D2), and the different capacitor electrode structures (either the electrode 210L extends or does not extend to the bottommost surface of the capacitor region).
Further, Applicant did not distinctly and specifically point out supposed errors in the restriction requirement. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Accordingly, the requirement is still deemed proper and is therefore made FINAL.
Claim Objections
Claim 3 is objected to because of the following informalities:
Claim 3 includes “a width of the first upper electrode structure in the first direction a nd (sic) a width of the first upper electrode structure in the second direction decrease t oward (sic) an upper surface of the first lower electrode structure” which has spaces in the words “and” and “toward”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20220139821A1 (“Hwang”) in view of US20200152623A1 (“Kocon”).
RE: Claim 1, Hwang discloses A semiconductor device (device in FIG. 27), comprising:
a first semiconductor structure (portion of structure in FIG. 27 including layer 456 and layers below layer 456) including a substrate (700), circuit devices (transistors formed on substrate 700, [0122], see FIG. 20) on the substrate, a lower interconnection structure (lower interconnect structure in 830, including 822, 812, 802, 782, 826, 816, 806, 786, [0126]-[0128]) electrically connected to the circuit devices, and a capacitor structure (492; the first conductive patterns 492 may serve as passive devices, e.g., capacitors, [0146]) on a same level as a level of at least a portion of the lower interconnection structure (FIG. 27 shows the capacitor structure 492 and the lower interconnection structure formed on same top surface/level of 710); and
a second semiconductor structure (portion of structure in FIG. 27 including layers above 456) on the first semiconductor structure and including a plurality of memory cells arranged three-dimensionally (memory cells, [0138]; The gate electrodes 402, 404 and 406, the channels 270 extending through the gate electrodes 402, 404 and 406, and the charge storage structures 260 between the channels 270 and the gate electrodes 402, 404 and 406 may form memory cells, [0138]; memory cells may be three-dimensionally stacked, [0003]),
wherein the lower interconnection structure includes
a lower contact (792, 796),
a lower line (802, 806) on the lower contact,
an upper contact (812, 816) on the lower line, and
an upper line (822, 826) on the upper contact.
Hwang does not explicitly disclose:
wherein the capacitor structure includes first electrode structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction,
second electrode structures positioned alternately alongside the first electrode structures and spaced apart from each other in the second direction, and
dielectric layers between the first electrode structures and the second electrode structures, and
wherein each of the first electrode structures and the second electrode structures includes
a first lower electrode structure and a second lower electrode structure on a same level as a level of at least one of the lower contact and the lower line, and
a first upper electrode structure and a second upper electrode structure on a same level as a level of at least one of the upper contact and the upper line.
In the same field of endeavor, Kocon discloses in FIG. 1 (see also Annotated FIG. 1 below):
an interconnection structure (162, 163, [0035]) includes
a lower contact (163 in layer 164),
a lower line (162 in layer 165) on the lower contact,
an upper contact (163 in layer 165) on the lower line, and
an upper line (162 in layer 166) on the upper contact,
wherein a capacitor structure (180, 181, [0034]) includes first electrode structures (left 182, 183 in 180 and left 182, 183 in 181 in FIG. 1) extending in a first direction (182 extends in Y-direction in FIG. 3) and spaced apart from each other in a second direction (X-direction in FIGs. 1, 3) intersecting the first direction,
second electrode structures (right 182, 183 in 180 and right 182, 183 in 181 in FIG. 1) positioned alternately alongside the first electrode structures and spaced apart from each other in the second direction, and
dielectric layers (dielectric material in layers 158, 164-167, [0035]; The dielectric material of the metallization layers 158, 164-167 provides a dielectric material with a thickness equal to the gap distance 184 between the generally parallel plates 191 and 192, [0035]) between the first electrode structures and the second electrode structures, and
wherein each of the first electrode structures and the second electrode structures includes
a first lower electrode structure (183 in layer 164, 182 in layer 165) and a second lower electrode structure (another 183 in layer 164, another 182 in layer 165 as shown in Annotated FIG. 1 below) on a same level as a level of at least one of the lower contact and the lower line, and
a first upper electrode structure (183 in layer 165, 182 in layer 166) and a second upper electrode structure (another 183 in layer 165, 182 in layer 166) on a same level as a level of at least one of the upper contact and the upper line.
Kocon further discloses the disclosed examples facilitate increased operating frequency to increase power density and improve circuit efficiency, [0019].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the lower interconnection structure and the capacitor structure to have the structures as taught by Kocon in order to increase power density and improve circuit efficiency.
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Annotated FIG. 1 of Kocon
RE: Claim 2, Hwang in view of Kocon discloses The semiconductor device of claim 1,
wherein the first upper electrode structure is electrically connected to the upper line through the first lower electrode structure and the upper contact (Annotated FIG. 1 of Kocon above shows the first upper electrode structure is electrically connected to the upper line through the first lower electrode structure and the upper contact, through physical connection and/or through capacitive coupling in 182, 183), and
wherein the second upper electrode structure is electrically connected to the upper line through the second lower electrode structure and the upper contact (Annotated FIG. 1 of Kocon above shows the second upper electrode structure is electrically connected to the upper line through the second lower electrode structure and the upper contact, through physical connection and/or through capacitive coupling in 182, 183).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hwang in view of Kocon as applied to claim 1 above, and further in view of US20190103353 A1 (“Liu”).
RE: Claim 3, Hwang in view of Kocon does not explicitly disclose The semiconductor device of claim 1,
wherein a width of the first upper electrode structure in the first direction and a width of the first upper electrode structure in the second direction decrease toward an upper surface of the first lower electrode structure.
However, in a similar field of endeavor, Liu discloses the conductive vias 120A and 120E are circular in a top down view. In such embodiments when the conductive vias 120A and 120E are circular, stress concentration can be reduced at the interface between the conductive vias 120A and 120E, [0032].
Liu further teaches a diameter of the openings 408 may continuously decrease in a direction towards the dielectric layer 118A/conductive vias 120A. A diameter of the conductive vias 120A may likewise continuously decrease towards the dielectric layer 118E/openings 408 (e.g., as a result of the patterning process described with respect to FIG. 4A), [0056], see FIG. 1A.
Accordingly, Liu teaches the vias 120A have diameters that decrease in the downward direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the vias 183 to have circular cross-sections with a diameter of the vias 183 decreasing in a downward direction as taught by Liu in order to reduce stress concentration as further taught by Liu. As a result, the first upper electrode structure 183, 182 would have a width in the first direction and a width in the second direction that decrease in a downward direction toward an upper surface of the first lower electrode structure.
Claim(s) 5, 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hwang in view of Kocon as applied to claim 1 above, and further in view of US6624040 B1 (“Ng”).
RE: Claim 5, Hwang in view of Kocon does not explicitly disclose The semiconductor device of claim 1,
wherein the first upper electrode structure includes a first upper electrode line and a first upper barrier surrounding a sidewall of the first upper electrode line,
wherein the first lower electrode structure includes a first lower electrode line and a first lower barrier surrounding a sidewall of the first lower electrode line,
wherein the first upper barrier extends from a same level as a level of an upper surface of the upper line to a same level as a level of a lower surface of the upper contact, and
wherein the first lower barrier extends from a same level as a level of an upper surface of the lower line to a same level as a level of a lower surface of the lower contact.
In the same field of endeavor, Ng discloses in FIG. 15:
an upper electrode structure (upper 52, 50 for capacitor 96/98/96, Col. 4, lines 58-62) includes a first upper electrode line (upper 52, Col. 3, lines 55-57) and a first upper barrier (upper barrier 50, Col. 3, line 45) surrounding a sidewall of the first upper electrode line,
wherein the first upper barrier (upper 50) extends from a same level as a level of an upper surface of an upper line (wider portion of upper 54 of interconnect 94; The copper layer 92, 94 forms interconnects to the capacitors and lower level logic interconnects, Col. 4, lines 35-40) to a same level as a level of a lower surface of an upper contact (narrower portion of upper 54 of interconnect 94 which are vias 55 shown in FIG. 7B; in the portion of the logic copper interconnect 54 shown in FIG. 7B, the lower portion is in the form of vias 55 rather than a continuous trench, Col. 3, lines 60-63);
a lower electrode structure (lower 52, 50 for capacitor 96/98/96) includes a first lower electrode line (lower 52) and a first lower barrier (lower barrier 50) surrounding a sidewall of the first lower electrode line,
wherein the first lower barrier (lower 50) extends from a same level as a level of an upper surface of the lower line (wider portion of lower 54 of interconnect 94) to a same level as a level of a lower surface of the lower contact (narrower portion of lower 54 which are vias 55 as shown in FIG. 7B).
Ng teaches object of the present invention is to provide a method for fabricating an increased capacitance metal-insulator-metal capacitor using an integrated copper dual damascene process, Col. 1, lines 60-65.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first upper electrode structure and first lower electrode structure to each have a barrier as taught by Ng in order to fabricate a capacitor with increased capacitance as further taught by Ng.
RE: Claim 11, Hwang in view of Kocon does not explicitly disclose The semiconductor device of claim 1,
wherein the upper line includes an upper conductive layer and an upper line barrier along a side surface and a lower surface of the upper conductive layer,
wherein the upper contact includes an upper contact plug and an upper contact barrier along a side surface and a lower surface of the upper contact plug,
wherein the lower line includes a lower conductive layer and a lower line barrier along a side surface and a lower surface of the lower conductive layer, and
wherein the lower contact includes a lower contact plug and a lower contact barrier along a side surface and a lower surface of the lower contact plug.
However, in the same field of endeavor, Ng discloses in FIG. 15:
an upper line (wider portion of upper 54 of interconnect 94 and barrier 50; The copper layer 92, 94 forms interconnects to the capacitors and lower level logic interconnects, Col. 4, lines 35-40) includes an upper conductive layer (copper layer 54, Col. 3, lines 55-57) and an upper line barrier (upper barrier 50, Col. 3, line 45) along a side surface and a lower surface of the upper conductive layer,
an upper contact (narrower portion of upper 54 of interconnect 94 which are vias 55 shown in FIG. 7B and barrier 50; in the portion of the logic copper interconnect 54 shown in FIG. 7B, the lower portion is in the form of vias 55 rather than a continuous trench, Col. 3, lines 60-63) includes an upper contact plug (copper in narrower portion of 54) and an upper contact barrier (upper 50) along a side surface and a lower surface of the upper contact plug,
a lower line (wider portion of lower 54 of interconnect 94 and barrier 50) includes a lower conductive layer (copper layer 54, Col. 3, lines 55-57) and a lower line barrier (lower 50) along a side surface and a lower surface of the lower conductive layer, and
a lower contact (narrower portion of lower 54 of interconnect 94 which are vias 55 shown in FIG. 7B and barrier 50) includes a lower contact plug (copper in narrower portion of 54) and a lower contact barrier (lower 50) along a side surface and a lower surface of the lower contact plug.
Ng teaches object of the present invention is to provide a method for fabricating an increased capacitance metal-insulator-metal capacitor using an integrated copper dual damascene process, Col. 1, lines 60-65.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the upper line, upper contact, lower line, lower contact to each have a barrier as taught by Ng in order to fabricate a capacitor with increased capacitance as further taught by Ng.
RE: Claim 12, Hwang in view of Kocon, Ng discloses The semiconductor device of claim 11,
wherein the lower conductive layer is integrated with and in direct contact with the lower contact plug (Ng Fig. 15 shows the wider lower conductive layer 54 is integrated with and in direct contact with the narrower lower contact plug 54), and wherein the lower line barrier is integrated with the lower contact barrier (Ng FIG. 15 shows the wider lower line barrier 50 is integrated with the narrower lower contact barrier 50).
RE: Claim 13, Hwang in view of Kocon, Ng discloses The semiconductor device of claim 12,
wherein the upper conductive layer is integrated with and in direct contact with the upper contact plug (Ng Fig. 15 shows the wider upper conductive layer 54 is integrated with and in direct contact with the narrower upper contact plug 54), and
wherein the upper line barrier is integrated with the upper contact barrier (Ng FIG. 15 shows the wider upper line barrier 50 is integrated with the narrower upper contact barrier 50).
Claim(s) 15-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kocon in view of Ng.
RE: Claim 15, Kocon discloses A semiconductor device (100 in FIG. 1), comprising:
a substrate (100) including a capacitor region (middle region that includes capacitor 180, 181, [0034]) and an interconnection region (regions that include line segments 162, vias 163 on left and right of middle region that includes 180, 181, [0032]) on both sides of the capacitor region;
a capacitor structure (180, 181, [0034]) including a first electrode structures (left 182, 183 in 180 and left 182, 183 in 181 in FIG. 1) extending in a first direction (182 extends in Y-direction in FIG. 3) and spaced apart from each other in a second direction (X-direction in FIGs. 1, 3) intersecting the first direction;
second electrode structures (right 182, 183 in 180 and right 182, 183 in 181 in FIG. 1) positioned alternately alongside the first electrode structures and spaced apart from each other in the second direction;
dielectric layers (dielectric material in layers 158, 164-167, [0035]; The dielectric material of the metallization layers 158, 164-167 provides a dielectric material with a thickness equal to the gap distance 184 between the generally parallel plates 191 and 192, [0035]) between the first electrode structures and the second electrode structures in the capacitor region;
a lower contact (163 in layer 164, see Annotated FIG. 1 below);
a lower line (162 in layer 165) on the lower contact;
an upper contact (163 in layer 165) on the lower line; and
an upper line (162 in layer 166) on the upper contact in the interconnection region,
wherein each of the first electrode structures and the second electrode structures includes
a first lower electrode structure (183 in layer 164, 182 in layer 165) and a second lower electrode structure (another 183 in layer 164, another 182 in layer 165 as shown in Annotated FIG. 1 below) on a same level as a level of the lower contact or the lower line, and
a first upper electrode structure (183 in layer 165, 182 in layer 166) and a second upper electrode structure (another 183 in layer 165, 182 in layer 166) on the upper contact or the upper line on a same level as a level of the upper line.
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Annotated FIG. 1 of Kocon
Kocun does not explicitly disclose:
wherein the first upper electrode structure includes a first upper electrode line and a first upper barrier surrounding a sidewall of the first upper electrode line,
wherein the first lower electrode structure includes a first lower electrode line and a first lower barrier surrounding a sidewall of the first lower electrode line,
wherein at least one of the first upper barrier or the first lower barrier extends from a same level as a level of an upper surface of the upper line to a same level as a level of a lower surface of the upper contact, or extends from a same level as a level of an upper surface of the lower line to a same level as a level of a lower surface of the lower contact.
In the same field of endeavor, Ng discloses in FIG. 15:
an first upper electrode structure (upper left 52, 50 for capacitor 96/98/96, Col. 4, lines 58-62) includes a first upper electrode line (upper 52, Col. 3, lines 55-57) and a first upper barrier (upper left barrier 50, Col. 3, line 45) surrounding a sidewall of the first upper electrode line,
a first lower electrode structure (lower left 52, 50 for capacitor 96/98/96) includes a first lower electrode line (lower 52) and a first lower barrier (lower left barrier 50) surrounding a sidewall of the first lower electrode line,
wherein at least one of the first upper barrier or the first lower barrier (upper left 50 or lower left 50 in the capacitor 96/98/96) extends from a same level as a level of an upper surface of an upper line (wider portion of upper 54 of interconnect 94) to a same level as a level of a lower surface of an upper contact (narrower portion of upper 54 which are vias 55 as shown in FIG. 7B), or extends from a same level as a level of an upper surface of the lower line to a same level as a level of a lower surface of the lower contact (this latter limitation is considered optional due to the presence of the word “or” when the first limitation is met; as the first limitation is met, the latter limitation is met).
Ng teaches object of the present invention is to provide a method for fabricating an increased capacitance metal-insulator-metal capacitor using an integrated copper dual damascene process, Col. 1, lines 60-65.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first upper electrode structure and first lower electrode structure to each have a barrier as taught by Ng in order to fabricate a capacitor with increased capacitance as further taught by Ng.
RE: Claim 16, Kocon in view of Ng discloses The semiconductor device of claim 15,
wherein the second upper electrode structure includes a second upper electrode line (From Ng: FIG. 15: upper right 52, 50 for capacitor 96/98/96, Col. 4, lines 58-62) and a second upper electrode barrier (From Ng: upper right barrier 50, Col. 3, line 45) surrounding a sidewall of the second upper electrode line,
wherein the second lower electrode structure includes a second lower electrode line (From Ng: lower right 52, 50 for capacitor 96/98/96) and a second lower electrode barrier (From Ng: lower right barrier 50) surrounding a sidewall of the second lower electrode line,
wherein at least one of the second upper electrode barrier or the second lower electrode barrier (In Ng: upper right 50 or lower right 50 in the capacitor 96/98/96) extends from the same level as a level of an upper surface of the upper line (wider portion of upper 54 of interconnect 94) to the same level as a level of a lower surface of the upper contact (narrower portion of upper 54 which are vias 55 as shown in FIG. 7B), or extends from the same level as a level of an upper surface of the lower line to the same level as a level of a lower surface of the lower contact (this latter limitation is considered optional due to the presence of the word “or” when the first limitation is met; as the first limitation is met, the latter limitation is met).
RE: Claim 17, Kocon in view of Ng discloses semiconductor device of claim 15,
wherein the upper line (From Ng: FIG. 15: wider portion of upper 54 of interconnect 94 and barrier 50; The copper layer 92, 94 forms interconnects to the capacitors and lower level logic interconnects, Col. 4, lines 35-40) includes an upper conductive layer (copper layer 54, Col. 3, lines 55-57) and an upper line barrier (upper barrier 50, Col. 3, line 45) along a side surface and a lower surface of the upper conductive layer,
wherein the upper contact (From Ng: FIG. 15: narrower portion of upper 54 of interconnect 94 which are vias 55 shown in FIG. 7B and barrier 50; in the portion of the logic copper interconnect 54 shown in FIG. 7B, the lower portion is in the form of vias 55 rather than a continuous trench, Col. 3, lines 60-63) includes an upper contact plug (copper in narrower portion of 54) and an upper contact barrier (upper 50) along a side surface and a lower surface of the upper contact plug,
wherein the lower line (From Ng: FIG. 15: wider portion of lower 54 of interconnect 94 and barrier 50) includes a lower conductive layer (copper layer 54, Col. 3, lines 55-57) and a lower line barrier (lower 50) along a side surface and a lower surface of the lower conductive layer, and
wherein the lower contact (From Ng: FIG. 15: narrower portion of lower 54 of interconnect 94 which are vias 55 shown in FIG. 7B and barrier 50) includes a lower contact plug (copper in narrower portion of 54) and a lower contact barrier (lower 50) along a side surface and a lower surface of the lower contact plug.
RE: Claim 18, Kocon in view of Ng discloses The semiconductor device of claim 17,
wherein the lower conductive layer is integrated with and in direct contact with the lower contact plug (Ng Fig. 15 shows the wider lower conductive layer 54 is integrated with and in direct contact with the narrower lower contact plug 54),
wherein the lower line barrier is integrated with the lower contact barrier (Ng FIG. 15 shows the wider lower line barrier 50 is integrated with the narrower lower contact barrier 50), and
wherein the upper conductive layer is integrated with and in direct contact with the upper contact plug (Ng Fig. 15 shows the wider upper conductive layer 54 is integrated with and in direct contact with the narrower upper contact plug 54), and
wherein the upper line barrier is integrated with the upper contact barrier (Ng FIG. 15 shows the wider upper line barrier 50 is integrated with the narrower upper contact barrier 50).
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hwang in view of Kocon.
RE: Claim 19, Hwang discloses A data storage system (device in FIG. 27), comprising:
a semiconductor storage device (semiconductor device in FIG. 27 which is a storage device corresponding to a cross-section of 2003 in FIGs. 2-3, [0155]; The filling pattern 280, the channel 270, the charge storage structure 260 and the capping pattern 290 may form a memory channel structure 490 having a pillar shape, which may correspond to the memory channel structures 3220 and 4220 shown in FIGS. 2 and 3, [0079]) including a substrate (700 in FIG. 27), circuit devices (transistors formed on substrate 700, [0122], see FIG. 20) on the substrate,
a lower interconnection structure (lower interconnect structure in 830, including 822, 812, 802, 782, 826, 816, 806, 786, [0126]-[0128]) electrically connected to the circuit devices, and a capacitor structure (492; the first conductive patterns 492 may serve as passive devices, e.g., capacitors, [0146]), memory cells (memory cells, [0138]), and an input/output pad (2210 in FIG. 2, [0041]) connected to the lower interconnection structure (Each semiconductor chip 2200 a may further include the input/output pad 2210 (refer to FIG. 2) electrically connected to the peripheral circuit wirings 4110 of the first structure 4100, [0056]; The fifth bonding pattern and the sixth to eighth bonding patterns 852, 854 and 856 may correspond to the first bonding structure 4150 shown in FIG. 3, [0131]; Accordingly, the lower interconnection structure is part of 2003 and therefore is connected to 2210); and
a controller (2002 in FIG. 2; The controller 2002 may write data in the semiconductor package 2003 or read data from the semiconductor package 2003, [0047]) electrically connected to the semiconductor storage device through the input/output pad and controlling the semiconductor storage device (The input/output pad 2210 may correspond to the input/output pad 1101 of FIG. 1, [0050]; The semiconductor device 1100 may communicate with the controller 1200 through an input/output pad 1101 electrically connected to the logic circuit 1130, [0041]; Accordingly, the controller 2002 would be electrically connected to 2003 through the input/output pad 2210),
wherein the lower interconnection structure is in an interconnection region (The fifth bonding pattern and the sixth to eighth bonding patterns 852, 854 and 856 may correspond to the first bonding structure 4150 shown in FIG. 3, [0131]; Accordingly, the lower interconnection structure is in an interconnection region 4100 in FIG. 3), and includes lower contacts (792, 796) on the circuit devices, lower lines (802, 806) on the lower contacts, upper contacts (812, 816) on the lower lines, and upper lines (822, 826) on the upper contacts.
Hwang does not explicitly disclose:
wherein the capacitor structure includes first electrode structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction,
second electrode structures positioned alternately alongside the first electrode structures and spaced apart from each other in the second direction, and
dielectric layers between the first electrode structures and the second electrode structures,
wherein each of the first electrode structures and the second electrode structures includes
a first lower electrode structure and a second lower electrode structure on a same level as a level of at least one of the lower contact and the lower line, and
a first upper electrode structure and a second upper electrode structure on a same level as a level of at least one of the upper contact and the upper line.
However, in the same field of endeavor, Kocon discloses in FIG. 1 (see Annotated FIG. 1 below):
lower contacts (163 in layer 164) on the circuit devices, lower lines (162 in layer 165) on the lower contacts, upper contacts (163 in layer 165) on the lower lines, and upper lines (162 in layer 166) on the upper contacts;
a capacitor structure (180, 181, [0034]) includes first electrode structures (left 182, 183 in 180 and left 182, 183 in 181 in FIG. 1) extending in a first direction (182 extends in Y-direction in FIG. 3) and spaced apart from each other in a second direction (X-direction in FIGs. 1, 3) intersecting the first direction,
second electrode structures (right 182, 183 in 180 and right 182, 183 in 181 in FIG. 1) positioned alternately alongside the first electrode structures and spaced apart from each other in the second direction, and
dielectric layers (dielectric material in layers 158, 164-167, [0035]; The dielectric material of the metallization layers 158, 164-167 provides a dielectric material with a thickness equal to the gap distance 184 between the generally parallel plates 191 and 192, [0035]) between the first electrode structures and the second electrode structures,
wherein each of the first electrode structures and the second electrode structures includes
a first lower electrode structure (183 in layer 164, 182 in layer 165) and a second lower electrode structure (another 183 in layer 164, another 182 in layer 165 as shown in Annotated FIG. 1 below) on a same level as a level of at least one of the lower contact and the lower line, and
a first upper electrode structure (183 in layer 165, 182 in layer 166) and a second upper electrode structure (another 183 in layer 165, 182 in layer 166) on a same level as a level of at least one of the upper contact and the upper line (163 in layer 165 or 162 in layer 166).
Kocon further discloses the disclosed examples facilitate increased operating frequency to increase power density and improve circuit efficiency, [0019].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the lower interconnection structure and the capacitor structure to have the structures as taught by Kocon in order to increase power density and improve circuit efficiency.
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Annotated FIG. 1 Kocon
RE: Claim 20, Hwang in view of Kocon discloses The data storage system of claim 19,
wherein the first upper electrode structure between the upper lines has a line shape extending in the first direction or a plate shape (Kocon FIG. 3 shows 182 has a line shape extending in the Y-direction), and
wherein the first upper electrode structure is spaced apart from the upper line in the first direction (Kocon FIG. 3 discloses 182 spaced apart from 162 in Y-direction), and is electrically connected to the upper line through the first lower electrode structure and the upper contact (Annotated FIG. 1 of Kocon above shows the first upper electrode structure is electrically connected to the upper line through the first lower electrode structure and the upper contact, through physical connection and/or through capacitive coupling in 182, 183).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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