DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in Korean Patent Application No. 10-2023-0089895, filed on 7/11/2023.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 5/17/2024 and 6/22/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Election/Restriction
It has been acknowledged that the applicant has elected without traverse Invention (Group I, claims 1-16), and in addition amended claims 4, 10, and 16 per the response dated on 8/9/2026. Currently claims 1-16 are present for examination.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The title of the invention has been suggested as, “SEMICONDUCTOR PACKAGE INCLUDING UNDER BUMP METALLIZATION STRUCTURES HAVING A T-TYPE SHAPE AND MANUFACTURING METHOD THEREOF”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 5-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Suk Embodiment 1 (US 2022/0077048 A1, Embodiment shown in Figs. 1A).
Regarding claim 1, Suk Embodiment 1 teaches a semiconductor package (semiconductor package 1, Figs. 1A, [0023]) comprising:
a first redistribution layer structure (redistribution substrate 100, Fig. 1A, [0024]) including a plurality of redistribution vias (vias of first conductive patterns 110S, 110G, and 110P, second conductive patterns 1205, 120G, and 120P, third conductive patterns 130S, 130G, and 130P, and fourth conductive patterns 140S, 140G, and 140P; Fig. 1A, [0026]) and a plurality of under bump metallization (UBM) structures (under-bump patterns 160, Fig. 1A, [0027]); and
a first semiconductor die (semiconductor chip 200, Fig. 1A, [0024]) on the first redistribution layer structure (redistribution substrate 100, Fig. 1A),
wherein each of the plurality of UBM structures (under-bump patterns 160, Fig. 1A) includes:
a UBM via (first part 161 of under-bump patterns 160, Fig. 1, [0027]); and
a UBM wire line (second part 162 of under-bump patterns 160, Figs. 1A and 1D) extending in a horizontal direction (first direction D1, Fig. 1A, [0027]) on the UBM via (first part 161, Figs. 1A and 1D) and electrically connecting one of the plurality of redistribution vias (via part 111, Fig. 1A, [0041]) and the UBM via (first part 161, Figs. 1A and 1D) in the horizontal direction (second direction D2, Fig. 1D).
Regarding claim 5, Suk Embodiment 1 teaches the semiconductor package (semiconductor package 1, Figs. 1A) of claim 1,
wherein the plurality of UBM structures include a plurality of ground UBM structures (ground under-bump pattern 160G, Fig. 1A), and
wherein UBM vias (first part 161 of ground under-bump pattern 160G, Fig. 1A) of the plurality of ground UBM structures (ground under-bump pattern 160G, Fig. 1A) are ground UBM vias (first part 161 of ground under-bump pattern 160G, Fig. 1A), and UBM wire lines (second part 162 of ground under-bump pattern 160G, Fig. 1A) of the plurality of ground UBM structures (ground under-bump pattern 160G, Fig. 1A) are ground UBM wire lines (second part 162 of ground under-bump pattern 160G, Fig. 1A, [0028]: “The second part 162 of the ground under-bump pattern 160G and the second part 162 of the power under-bump pattern 160P each serve as a routing or line part.”).
Regarding claim 6, Suk Embodiment 1 teaches the semiconductor package (semiconductor package 1, Figs. 1A) of claim 5, wherein each of the plurality of ground UBM structures (ground under-bump pattern 160G, Fig. 1A) includes:
one or more ground UBM vias (first part 161 of ground under-bump pattern 160G, Fig. 1A); and
one ground UBM wire line (second part 162 of ground under-bump pattern 160G, Fig. 1A) corresponding to the one or more ground UBM vias (first part 161 of ground under-bump pattern 160G, Fig. 1A).
Regarding claim 7, Suk Embodiment 1 teaches the semiconductor package (semiconductor package 1, Figs. 1A) of claim 6,
wherein the one or more ground UBM vias (first part 161 of ground under-bump pattern 160G, Fig. 1A) is a plurality of ground UBM vias (first part 161 of ground under-bump pattern 160G, Fig. 1A), and
wherein the one ground UBM wire line (second part 162 of ground under-bump pattern 160G, Fig. 1A) merges the plurality of ground UBM vias (first part 161 of ground under-bump pattern 160G, Fig. 1A).
Regarding claim 8, Suk Embodiment 1 teaches the semiconductor package (semiconductor package 1, Figs. 1A) of claim 1,
wherein the plurality of UBM structures (under-bump patterns 160, Fig. 1A) include a plurality of power UBM structures (power under-bump pattern 160S, Fig. 1A, [0028]), and
wherein UBM vias (first part 161 of power under-bump pattern 160S, Fig. 1A) of the plurality of power UBM structures (power under-bump pattern 160S, Fig. 1A) are power UBM vias (first part 161 of power under-bump pattern 160S, Fig. 1A), and UBM wire lines (second part 161 of power under-bump pattern 160S, Fig. 1A) of the plurality of power UBM structures (power under-bump pattern 160S, Fig. 1A) are power UBM wire lines (second part 161 of power under-bump pattern 160S, Fig. 1A, [0028]: “The second part 162 of the ground under-bump pattern 160G and the second part 162 of the power under-bump pattern 160P each serve as a routing or line part.”).
Regarding claim 9, Suk Embodiment 1 teaches the semiconductor package (semiconductor package 1, Figs. 1A) of claim 1, wherein each UBM structure (under-bump patterns 160, Fig. 1A) has a T-type shape (Fig. 1A: in the cross-section shown in Fig. 1A, each under-bump pattern 160 has a T-shape, some with two T-shapes connected) by combining a lower UBM via (first part 161 of under-bump patterns 160, Fig. 1A) that vertically (vertical direction in Fig. 1A) extends and an upper UBM wire line (second part 162 of under-bump patterns 160, Fig. 1A) that horizontally (horizontal direction in Fig. 1A) extends.
Regarding claim 10, Suk Embodiment 1 teaches the semiconductor package (semiconductor package 1, Figs. 1A) of claim 1,
wherein the UBM wire line (under-bump patterns 160, Fig. 1A) includes a first portion (see first portion in Illustrative Fig. 1, which is an annotated version of Fig. 1A) extending in one direction (towards left in Illustrative Fig. 1) and in the horizontal direction (horizontal direction in Illustrative Fig. 1), and a second portion (second portion, Illustrative Fig. 1) extending in the other direction (towards right in Illustrative Fig. 1) opposite to the one direction (towards left in Illustrative Fig. 1) and in the horizontal direction (horizontal direction in Illustrative Fig. 1), based on the UBM via (UBM via, Illustrative Fig. 1), and
wherein a length of the first portion (length 1, Illustrative Fig. 1) in the horizontal direction (horizontal direction in Illustrative Fig. 1) and a length of the second portion (length 2, Illustrative Fig. 1) in the horizontal direction (horizontal direction in Illustrative Fig. 1) are different (Illustrative Fig. 1: length 2 is longer than length 2).
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Claims 11-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Suk Embodiment 2 (US 2022/0077048 A1, Embodiment shown in Fig. 5).
Regarding claim 11, Suk Embodiment 2 teaches a semiconductor package (semiconductor package 4, Fig. 5, [0165]) comprising:
a first redistribution layer structure (redistribution substrate 100, Fig. 5, [0024]) including a plurality of under bump metallization (UBM) structures (under-bump patterns 160, Fig. 5, [0027]), a plurality of redistribution vias (vias of first conductive patterns 110S, 110G, and 110P; Fig. 5, [0026]), a plurality of redistribution lines (top portions of first conductive patterns 110S, 110G, and 110P; Fig. 5) on the plurality of UBM structures (under-bump patterns 160, Fig. 5), and a dielectric layer (first dielectric layer 101 and second dielectric layer 102, Fig. 5, [0026]), wherein the dielectric layer (second dielectric layer 102, Fig. 5) surrounds the plurality of UBM structures (under-bump patterns 160, Fig. 5), the plurality of redistribution vias (vias of first conductive patterns 110S, 110G, and 110P; Fig. 5), and the plurality of redistribution lines (top portions of first conductive patterns 110S, 110G, and 110P; Fig. 5);
a plurality of connection members (solder patterns 500, Fig. 5, [0024]) on a lower surface (bottom surface, Fig. 5) of the first redistribution layer structure (redistribution substrate 100, Fig. 5);
a first semiconductor die (first semiconductor chip 210A, Fig. 5, [0135]) on the first redistribution layer structure (redistribution substrate 100, Fig. 5);
a plurality of conductive posts (conductive structure 310, Fig. 5, [0151]) on the first redistribution layer structure (redistribution substrate 100, Fig. 5);
a molding material (molding layer 400, Fig. 5, [0080]) disposed on the first redistribution layer structure (redistribution substrate 100, Fig. 5) and molding the first semiconductor die (first semiconductor chip 210A, Fig. 5) and the plurality of conductive posts (conductive structure 310, Fig. 5);
a second redistribution layer structure (upper redistribution layer 600, Fig. 5, [0156]) on the molding material (molding layer 400, Fig. 5); and
a second semiconductor die (upper semiconductor chip 720, Fig. 5, [0158]) on the second redistribution layer structure (upper redistribution layer 600, Fig. 5),
wherein each of the plurality of UBM structures (under-bump patterns 160, Fig. 5) includes:
a UBM via (first part 161 of under-bump patterns 160, Fig. 5, [0027]); and
a UBM wire line (second part 162 of under-bump patterns 160, Fig. 5) extending in a horizontal direction (horizontal direction in Fig. 5) on the UBM via (first part 161) and electrically connecting one of the plurality of redistribution vias (vias of first conductive patterns 110S, 110G, and 110P; Fig. 5) and the UBM via (first part 161 of under-bump patterns 160, Fig. 5) in the horizontal direction (horizontal direction in Fig. 5: redistribution vias and UBM vias are shifted in horizontal direction with respect to each other).
Regarding claim 12, Suk Embodiment 2 teaches the semiconductor package (semiconductor package 4, Fig. 5) of claim 11, further comprising:
a seed metal layer (under-bump seed pattern 170, Fig. 6, [0026]) between a side wall of the UBM via (left and right side walls of first part 161 of under-bump patterns 160 in Fig. 5) and the dielectric layer (first dielectric layer 101 and second dielectric layer 102, Fig. 5), and between a lower surface of the UBM wire line (lower surface of second part 162 of under-bump patterns 160 in Fig. 5) and the dielectric layer (first dielectric layer 101 and second dielectric layer 102, Fig. 5).
Regarding claim 13, Suk Embodiment 2 teaches the semiconductor package (semiconductor package 4, Fig. 5) of claim 11, wherein the first semiconductor die (first semiconductor chip 210A, Fig. 5) includes a system on chip (SoC) ([0139]: “the first semiconductor chip 210 may be … a system-on-chip (SOC)”).
Regarding claim 14, Suk Embodiment 2 teaches the semiconductor package (semiconductor package 4, Fig. 5) of claim 11, wherein the second semiconductor die (upper semiconductor chip 720, Fig. 5) includes a memory semiconductor ([0159]: “The upper semiconductor chip 720 includes integrated circuits that may include a memory circuit”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Suk Embodiment 1 (US 2022/0077048 A1, Embodiment shown in Fig. 1A) as applied to claims 1 and 5-10 above, and further in view of Suk (US 2022/0077048 A1).
Regarding claim 2, Suk Embodiment 1 teaches the semiconductor package (semiconductor package 1, Figs. 1A) of claim 1,
wherein the plurality of UBM structures (under-bump patterns 160, Fig. 1A) include a plurality of signal UBM structures (signal under-bump pattern 160S, Fig. 1A, [0028]), and
wherein UBM vias (first part 161 of signal under-bump pattern 160S, Fig. 1A) of the plurality of signal UBM structures (signal under-bump pattern 160S, Fig. 1A) are signal UBM vias (first part 161 of signal under-bump pattern 160S, Fig. 1A).
Suk Embodiment 1, however, does not teach that UBM wire lines (second part 162 of signal under-bump pattern 160S, Fig. 1A) of the plurality of signal UBM structures (signal under-bump pattern 160S, Fig. 1A) are signal UBM wire lines.
Suk, however, discloses that “the second part 162 of the under-bump pattern 160 serves as a routing or line part. For example, the second part 162 of the under-hump pattern 160 may be a pathway that horizontally transmits an electric signal received from the solder pattern 500 connected thereto.” ([0027]), and “the second part 162 of the under-bump pattern 160 is a routing or line part, there may be a reduction in the number of stacked conductive patterns 110S, 110B, 110P, 120S, 120G, 120P, 130S, 130G, 130P, 140S, 140G, and 140P. Accordingly, the semiconductor package 1 becomes more compact.”
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the number of stacked conductive patterns, and thereby the thickness of the semiconductor package, can be reduced by using the second part 162S of the signal under-bump pattern 160S in the semiconductor package of Suk Embodiment 1 as a signal UBM wire line. It would have been also obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that even though Suk Embodiment 1 does not use the signal under-bump pattern as a wire line, Suk does not teach away or discourage usage of the signal under-bump pattern as a wire line ([0033]: ”the signal under-bump pattern 160S have a circular shape in a plan view, hut embodiments of the present inventive concepts are not limited thereto”) (see also MPEP 2123(II): Disclosed examples and preferred embodiments do not constitute a teaching away from a broader disclosure or nonpreferred embodiments). Thus, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the semiconductor package of Suk Embodiment 1 to use the second parts 162 of the signal under-bump patterns 160S in the semiconductor package of Suk Embodiment 1 as signal UBM wire lines, to reduce the number of layers, and thereby also reducing device size and simplifying the manufacturing (Suk, [0029]). Furthermore. Suk Embodiment 1 already teaches that the ground under-bump patterns 160G and the power under-bump patterns 160P are used as UBM wire lines (0028]: “The second part 162 of the ground under-bump pattern 160G and the second part 162 of the power under-bump pattern 160P each serve as a routing or line part.”). Applying the same approach to the signal under-bump pattern 160S, which leads to the predictable result of improving the device further by reducing the number of layers, presents obviousness under KSR (see MPEP 2143(I)(D)).
Regarding claim 3, Suk Embodiment 1 in view of Suk teaches the semiconductor package of claim 2, wherein
Suk Embodiment 1 further teaches that each of the plurality of signal UBM structures (signal under-bump pattern 160S, Fig. 1A) includes:
one signal UBM via (first part 161 of signal under-bump pattern 160S, Fig. 1A); and
one signal UBM wire line (second part 161 of signal under-bump pattern 160S, Fig. 1A) corresponding to the one signal UBM via (first part 161 of signal under-bump pattern 160S, Fig. 1A).
Regarding claim 4, Suk Embodiment 1 in view of Suk teaches the semiconductor package of claim 2,
The combination of Suk Embodiment 1 in view of Suk (the signal under-bump pattern 160S of Suk Embodiment 1 modified by further teachings of Suk, see claim 2 rejection above) further teaches that the signal UBM wire lines (second part 162 of signal under-bump pattern 160S) has an elongated shape (the shape of the second part 162 of signal under-bump pattern 160S modified to extend horizontally like second part 162 of ground under-bump pattern 160G and second part 162 of power under-bump pattern 160P to route the signals horizontally; [0027]: “the second part 162 of the under-bump pattern 160 serves as a routing or line part. For example, the second part 162 of the under-hump pattern 160 may be a pathway that horizontally transmits an electric signal received from the solder pattern 500 connected thereto”).
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Suk Embodiment 2 (US 2022/0077048 A1, Embodiment shown in Fig. 5) as applied to claims 11-14 above and further in view of Tsai (US 2021/0050295 A1).
Regarding claim 15, while Suk Embodiment 2 teaches the semiconductor package of claim 11,
Suk Embodiment 2 does not teach that a ratio of a thickness of the first redistribution layer structure in a vertical direction to a thickness of the second redistribution layer structure in the vertical direction is about 7:5.
Tsai, on the other hand, teaches a semiconductor package (package 400, Figs. 4E-H, [0061]) comprising a first redistribution layer structure (first-side redistribution structure 106, Fig. 4H (see Fig. 4E for the label), [0025]), a first semiconductor die (integrated circuit die 50, Fig. 4H (see Fig. 4B for the label), [0013]), a second redistribution layer structure (second-side redistribution structure 206, Fig. 4H (see Fig. 4E for the label), [0045]), and a second semiconductor die (additional devices 510, Fig. 4, [0066]), wherein a ratio of a thickness of the first redistribution layer structure (thickness T1 of first-side redistribution structure 106, [0049], Fig. 4A) in a vertical direction (vertical direction in Fig. 4H) to a thickness of the second redistribution layer structure (thickness T2 of second-side redistribution structure 206 ([0049], Fig. 4A) in the vertical direction (vertical direction in Fig. 4H) is about 7:5 ([0049]: “The ratio of thickness T2 to thickness T1 may be about 0.3 to about 3.”).
Therefore, the ratio provided by the prior art falls within the range for the ratio provided in the claimed invention, and a prima facie case of obviousness exists (see MPEP 2144.05(I)). Tsai also discloses that a ratio in the range given by Tsai provides suitable stiffness to prevent or reduce warpage due to the differences in the coefficient of thermal expansions ([0049]). Accordingly, the ratio can be optimized by routine experimentation to achieve desired mechanical stiffness and device performance ([0049]), and a person of ordinary skill in the art before the effective filing date of the claimed invention would have had a reasonable expectation of success to arrive at a ratio 7:5 in the semiconductor package of Suk Embodiment 2, in order to achieve a desired mechanical stiffness and device performance (see MPEP 2144.05(II)).
Regarding claim 16, while Suk Embodiment 2 in view of Tsai teaches the semiconductor package of claim 15,
Suk Embodiment 2 does not teach that the thickness of the first redistribution layer structure in the vertical direction is about 30 ㎛ to about 40 ㎛.
Tsai, on the other hand, teaches that the thickness of the first redistribution layer structure (thickness T1 of first-side redistribution structure 106, [0049], Fig. 4A) in the vertical direction is about 30 ㎛ to about 40 ㎛ ([0039]: “about 20 μm to about 100 μm”).
Therefore, the range for the thickness of the first distribution layer structure provided by the prior art covers the range of the thickness of the first redistribution layer structure provided in the claimed invention, and a prima facie case of obviousness exists (see MPEP 2144.05(I)). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that a thicker redistribution layer structure provides better stiffness ([0049]) but may increase signal lengths and reduce device performance ([0049]). Accordingly, the thickness of the first redistribution layer structure can be optimized by routine experimentation to achieve desired mechanical stiffness and device performance ([0049]), and therefore, the thickness values provided do not hold an inventive subject matter (see MPEP 2144.05(II)).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Choi (US 2022/0157702 A1) teaches a semiconductor package with T-shaped under bump metallization structures, which is relevant to all claims.
Jeon (US 2022/0077041 A1) teaches a semiconductor package with T-shaped under bump metallization structures, which is relevant to all claims.
Lee (US 2021/0111114 A1) teaches a semiconductor package with T-shaped under bump metallization structures, which is relevant to all claims.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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