DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5 and 7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
For claim 1, the recitation “in response to latch circuit latching” on the last two lines of the claim is indefinite because it appears that “latch circuit” in the above phrase is unclear antecedent basis, and it is not clear if applicant means “in response to the latch circuit latching”. Clarification and/or appropriate correction is required.
Claims 2-5 and 7 are indefinite because they depend on claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 15 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Danjo (US 2013/0176156).
For claim 15, Figure 7 of Danjo teaches a method for performing a dynamic comparison, comprising: amplifying (NT15-NT17, PT14-PT15) a difference between a first differential input (VIP) and a second differential input (VIN) to generate a first differential amplifier output (DP) and a second differential amplifier output (DN); driving a gate of a first transistor (NT13) included in a first leg (NT11-PT11, NT13) of a latch circuit (NT11-NT14, PT11-PT12) with the first differential amplifier output (DP); driving a gate of a second transistor (NT14) included in a second leg (NT12-PT12, NT14) of the latch circuit (NT11-NT14, PT11-PT12) with the second differential amplifier output (DN); providing a first supplemental current (current of NT31) to a first differential output (OP) of the latch circuit (NT11-NT14, PT11-PT12) with a first boost transistor (NT31) having a gate coupled to the first differential amplifier output (OP), the first supplemental current (current of NT31) supplementing a first drive current (current of NT13) provided to the first leg (NT11-PT11, NT13) by the first transistor (NT13); providing a second supplemental current (current of NT32) to a second differential output (ON) of the latch circuit (NT11-NT14, PT11-PT12) with a second boost transistor (NT32) having a gate coupled to the second differential amplifier output (DN); the second supplemental current (current of NT32) supplementing a second drive current (current of NT14) provided to the second leg (NT12-PT12, NT14) by the second transistor (NT14); latching the first and second differential outputs (OP and ON) of the latch circuit (NT11-NT14, PT11-PT12) based on the first and second differential amplifier outputs (DP and DN); detecting (by 20, where 20 is shown in Figure 9) whether the first and second differential outputs of the latch circuit (OP and ON) have been latched during an active phase of the latch circuit (NT11-NT14, PT11-PT12); and blocking (by SW31 and SW32) the first supplemental current (current NT31) and the second supplemental current (current NT32) in response to detecting that the first and second differential outputs (OP and ON) of the latch circuit (NT11-NT14, PT11-PT12)have been latched.
For claim 17, Figures 7 and 9 of Danjo teaches wherein detecting (by using 20, where 20 is shown in Figure 9) wherein detecting whether the first and second differential outputs (OP and ON) of the latch circuit (NT11-NT14, PT11-PT12) have been latched comprises performing a logical-OR function (25, see Figure 9) on first and second differential outputs (OP and ON) of the latch circuit (NT11-NT14, PT11-PT12).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over Danjo (US 2013/0176156) in view of Li et al. (US 2023/0344346 A1).
For claim 1, Figure 7 of Danjo teaches a comparator, comprising: an amplifier circuit (NT15-NT17, PT14-PT15) configured to amplify a difference between a first differential input (VIP) and a second differential input (VIN) during an active phase of the comparator; a latch circuit (NT11-NT14, PT11-PT13) comprising: a first transistor (NT13) coupled to a first differential amplifier output (DP) of the amplifier circuit and configured to drive a first leg (NT11-PT11, NT13) of the latch circuit (NT11-NT14, PT11-PT12) with a first drive current (current of NT13); and a second transistor (NT14) coupled to a second differential amplifier output (DN) of the amplifier circuit and configured to drive a second leg (NT12-PT12, NT14) of the latch circuit (NT11-NT14, PT11-PT12) with a second drive current (current of NT14); and wherein the first leg (NT11-PT11, NT13) and the second leg (NT12-PT12, NT14) are configured to latch a first differential output (OP) and a second differential output (ON) of the latch circuit (NT11-NT14, PT11-PT12) during the active phase; and a boost circuit (31-32) comprising: a first boost transistor (NT31) coupled to the first differential amplifier output (DP) and configured to provide a first supplemental current (current of NT31) to the first differential output (OP) of the latch circuit (NT11-NT14, PT11-PT12) to supplement the first drive current (current of NT13) during the active phase; a first switch (SW1) coupled in series with the first boost transistor (NT31) and configured to block the first supplemental current (current NT31) in response to the latch circuit latching (the output of logic block 20 controlling the switch); a second boost transistor (NT32) coupled to the second differential amplifier output (DN) and configured to provide a second supplemental current (current NT32) to the second differential output (ON) of the latch circuit (NT11-NT14, PT11-PT12) to supplement the second drive current (current NT32) during the active phase; and a second switch (SW2) coupled in series with the second boost transistor (NT32) and configured to block the second supplemental current (current of NT32) in response to latch circuit latching (the output of logic block 20 controlling the switch). Figure 7 of Danjo does not teaches the first switch (SW31) and the second switch (SW32) are a first pass transistor and a second pass transistor, respectively. However, Figures 4A-4D of Li et al. each teaches a switch is form by passing transistor (see Figures 4A-4D, [0090]). Therefore, it would have been obvious to one having ordinary skilled in the art at the time before the invention was effectively filed to modify the circuit in Figure 7 of Danjo by specifically using first and second pass transistors as taught in Figures 4A-4D of Li et al. for the broad first and second switches (SW31 and SW32, Figure 7 of Danjo) because the use of a pass transistor for a switch is old and well-known, and the use of pass transistors in the circuitry provides the purpose of having the circuitry to be fully integrated using MOSFET technology for low power and high speed operations. Thus, this combination/modification meets all the limitations of claim 1 because the first and second switches are now first and second pass transistors, respectively.
For claim 2, Figure 7 of Danjo in the above combination/modification teaches a logic circuit (20, also see Figure 9) including: a first input (OP) coupled to the first differential output (OP) of the latch circuit (NT11-NT14, PT11-PT12); a second input (ON) coupled to the second differential output (ON) of the latch circuit (NT11-NT14, PT11-PT12); and an output (TO 31, TO 32) configured to indicate whether the latch circuit (NT11-NT14, PT11-PT12) has latched the first and second differential outputs (OP and ON) of the latch circuit (NT11-NT14, PT11-PT12).
For claim 3, it is seen in the above combination/modification (Figure 7 of Danjo in view of Li et al.) teaches a gate of the first pass transistor (SW1 that is replaced by a transistor) is coupled to the output of the logic circuit (20) and a gate of the second pass transistor (SW2 that is replaced by a transistor) is coupled to the output of the logic circuit (20).
For claim 4, Figures 7 and 9 of Danjo in the above combination/modification (Figure 7 of Danjo in view of Li et al.) teaches the logic circuit (20, also see Figure 9) comprises an OR-gate (25, see Figure 9).
For claim 8, Figure 7 of Danjo teaches a dynamic comparator, comprising: an amplifier circuit (NT15-NT17, PT14-PT15) comprising: a first differential input (VIP) and a second differential input (VIN); a first differential amplifier output (DP) and a second differential amplifier output (DN); and a clock input (CLK) configured to receive a clock signal (CLK) with a first state corresponding to an inactive phase of the dynamic comparator and a second state corresponding to an active phase of the dynamic comparator, the amplifier circuit (NT15-NT17, PT14-PT15) configured to be inactive during the first state of the clock signal (CLK) and configured to amplify a difference between the first differential input (VIP) and the second differential input (VIN) during the second state of the clock signal (CLK); a latch circuit (NT11-NT14, PT11-PT12) comprising: a first transistor (NT13) having a gate coupled to the first differential amplifier output (DP), the first transistor (NT13) configured to drive a first leg (NT11-PT11, NT13) of the latch circuit (NT11-NT14, PT11-PT12) with a first drive current (current NT13); and a second transistor (NT14) having a gate coupled to the second differential amplifier output (DN), the second transistor (NT14) configured to drive a second leg (NT12-PT12, NT14) of the latch circuit (NT11-NT14, PT11-PT12) with a second drive current (current NT14); and wherein the first leg (NT11-PT11, NT13) and the second leg (NT12-PT12, NT14) are configured to latch a first differential output (OP) and a second differential output (ON) of the latch circuit (NT11-NT14, PT11-PT12) during the active phase of the dynamic comparator in response to the first and second differential amplifier outputs (DP and DN); and a boost circuit (31-32) comprising: a first boost transistor (NT31) having a gate coupled to the first differential amplifier output (DP), the first boost transistor (NT31) configured to provide a first supplemental current to the first differential output (OP) of the latch circuit (NT11-NT14, PT11-PT12) to supplement the first drive current (current NT13) during the active phase; a first switch (SW1) coupled in series with the first boost transistor (NT31) and configured to block the first supplemental current (current NT31) in response to the latch circuit latching (the output of logic block 20 controlling the switch) a second boost transistor (N32) having a gate coupled to the second differential amplifier output (DN), the second boost transistor (NT32) configured to provide a second supplemental current to the second differential output (ON) of the latch circuit (NT11-NT14, PT11-PT12) to supplement the second drive current (current NT14) during the active phase; and a second switch (SW2) coupled in series with the second boost transistor (NT32) and configured to block the second supplemental current (current of NT32) in response to latch circuit latching (the output of logic block 20 controlling the switch). Figure 7 of Danjo does not teaches the first switch (SW31) and the second switch (SW32) are a first pass transistor and a second pass transistor, respectively. However, Figures 4A-4D of Li et al. each teaches a switch is form by passing transistor (see Figures 4A-4D, [0090]). Therefore, it would have been obvious to one having ordinary skilled in the art at the time before the invention was effectively filed to modify the circuit in Figure 7 of Danjo by specifically using first and second pass transistors as taught in Figures 4A-4D of Li et al. for the broad first and second switches (SW31 and SW32, Figure 7 of Danjo) because the use of a pass transistor for a switch is old and well-known, and the use of pass transistors in the circuitry provides the purpose of having the circuitry to be fully integrated using MOSFET technology for low power and high speed operations. Thus, this combination/modification meets all the limitations of claim 8 because the first and second switches are now first and second pass transistors, respectively.
For claim 9, Figure 7 of Danjo in the above combination/modification as discussed in claim 8 teaches a logic circuit (20, also see Figure 9) including: a first input (OP) coupled to the first differential output (OP) of the latch circuit (NT11-NT14, PT11-PT12); a second input (ON) coupled to the second differential output (ON) of the latch circuit (NT11-NT14, PT11-PT12); and an output (TO 31, TO 32) configured to indicate whether the latch circuit (NT11-NT14, PT11-PT12) has latched the first and second differential outputs (OP and ON) of the latch circuit (NT11-NT14, PT11-PT12).
For claim 10, it is seen in the above combination/modification (Figure 7 of Danjo in view of Li et al. as discussed in claim 8 above) teaches a gate of the first pass transistor (SW1 that is replaced by a transistor) is coupled to the output of the logic circuit (20) and a gate of the second pass transistor (SW2 that is replaced by a transistor) is coupled to the output of the logic circuit (20).
For claim 11, Figures 7 and 9 of Danjo teaches the logic circuit (20, also see Figure 9) comprises an OR-gate (25, see Figure 9).
Claims 5, 7, 12, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Danjo (US 2013/0176156) in view of Li et al. (US 2023/0344346 A1) as applied to claims 1-4 and 8-11 above, and further in view of Ding et al. (CN 108832916 A).
For claims 5 and 12, the combination/modification (Danjo in view of Li et al.) as discussed in claims 1 and 8 above) teaches all the limitations of these claims except for the comparator further comprising a reset circuit including a plurality of reset transistors configured to drive a respective plurality of nodes of the latch circuit to a reset voltage level during an inactive phase of the comparator. However, Figure 4 of Ding et al. teaches a reset circuit (M13-M14) including a plurality of reset transistors (M13-M14) configured to drive a respective plurality of nodes (nodes COP, CON) of the latch circuit (M7-M12) to a reset voltage level (VDD) during an inactive phase of the comparator. Therefore, it would have been obvious to one having ordinary skilled in the art at the time before the invention was effectively filed to modify the above combination/modification circuit (Figure 7 of Danjo in view of Li et al as discussed in claims 1 and 8 above) to include the reset circuit (M13-M14), as taught in Figure 4 of Ding et al., including a plurality of reset transistors (M13-M14) configured to drive a respective plurality of nodes (nodes COP, CON) of the latch circuit (NT11-NT14, PT11-PT12) to a reset voltage level (power supply voltage VDD) during an inactive phase of the comparator for the purpose of reducing the power consumption of the comparator circuitry. Thus, this combination/modification meets all the limitations of claims 5 and 12.
For claims 7 and 14, Figure 4 of Ding et al. in the above combination/modification as discussed in claims 5 and 12 teaches wherein each of the plurality of reset transistors (M13, M14) is configured to be driven by one of the first differential amplifier output (FN) and the second differential amplifier output (FP), so when combined and modified, the combination/modification as discussed in claims 5 and 15 teaches each of the plurality of reset transistors (M13, M14) is configured to be driven by one of the first differential amplifier output (DP) and the second differential amplifier output (DN).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Danjo (US 2013/0176156) in view of Ding et al. (CN 108832916 A).
For claim 19, Figure 7 of Danjo (as discussed in claim 15above) teaches all the limitations of this claims except for driving a plurality of nodes of the latch circuit to a reset voltage level during an inactive phase of the latch circuit. However, Figure 4 of Ding et al. teaches a reset circuit (M13-M14) including a plurality of reset transistors (M13-M14) configured to drive a respective plurality of nodes (nodes COP, CON) of the latch circuit (M7-M12) to a reset voltage level (VDD) during an inactive phase of the latch circuit. Therefore, it would have been obvious to one having ordinary skilled in the art at the time before the invention was effectively filed to modify the circuit in Figure 7 of Danjo (as discussed in claim 15 above) to include the reset circuit (M13-M14), as taught in Figure 4 of Ding et al., including a plurality of reset transistors (M13-M14) configured to drive a respective plurality of nodes (nodes COP, CON) of the latch circuit (NT11-NT14, PT11-PT12) to a reset voltage level (power supply voltage VDD) during an inactive phase of the latch circuit for the purpose of reducing the power consumption of the circuitry. Thus, this combination/modification meets all the limitations of claim 19 including the limitations driving a plurality of nodes (OP, ON) of the latch circuit to a reset voltage level (power supply VDD level) during an inactive phase of the latch circuit.
For claim 20, Figure 4 of Ding et al. in the above combination/modification as discussed in claim 19 teaches wherein each of the plurality of reset transistors (M13, M14) is configured to be driven by one of the first differential amplifier output (FN) and the second differential amplifier output (FP), so when combined and modified, the combination/modification as discussed in claim 19 teaches driving a gate of each of a plurality of reset transistors (M13, M14) with one of the first differential amplifier output (DP) and the second differential amplifier output (DN) during the inactive phase of the latch circuit.
Response to Arguments
Applicant's arguments filed 01/05/26 have been fully considered but they are not persuasive.
Applicant argues that: the cited art fails to disclose or suggest a boost circuit comprising “a first boost transistor coupled to the first differential amplifier output and configured to provide a first supplemental current to the first differential output of the latch circuit to supplement the first drive current during the active phase,” “a first pass transistor coupled in series with the first boost transistor and configured to block the first supplemental current in response to the latch circuit latching,” “a second boost transistor coupled to the second differential amplifier output and configured to provide a second supplemental current to the second differential output of the latch circuit to supplement the second drive current during the active phase,” and “a second pass transistor coupled in series with the second boost transistor and configured to block the second supplemental current in response to latch circuit latching,”. The Examiner contends that Danjo discloses a "first transistor (NT13) ... configured to drive a first leg (NT11-PT11, NT 13) of the latch circuit," and a boost circuit with "a first boost transistor (NT31) coupled to the first differential amplifier output (DP) and configured to provide a first supplemental current to the first differential output (OP) of the latch circuit." Office Action at 8. The Examiner likewise contends that Danjo discloses a "second transistor (NT14) ... configured to drive a second leg (NT12-PT12, NT14) of the latch circuit," and a boost circuit with a "a second boost transistor (NT32) coupled to the second differential amplifier output (DN) and configured to provide a second supplemental current to the second differential output (ON) of the latch circuit." Office Action at 8. However, the NT31 and NT32 do not provide currents that are supplemental to the drive currents provided by NT13 and NT14 to the first and second legs of Danjo's latch circuit. For example, NT31 has a source coupled (via SW31) to the first differential output (OP) while NT 13 has a drain coupled to the first differential output (OP). See Danjo at Fig. 7. Similarly, NT32 has a source coupled (via SW32) to the second differential output (ON) while NT14 has a drain coupled to the second differential output (ON). See Danjo at Fig. 7. Accordingly, any current provided by NT31 and NT32 will oppose the drive currents respectively provided by NT13 and NT14 to the first and second legs of the Danjo's latch circuit. Indeed, the purpose of NT31 and NT32 is to provide a means for correcting any input offset errors in Danjo's circuit. See Danjo at [0051], [0056], Fig. 7, Fig. 8. This is a much different structure and function than the boost circuits used to provide supplemental currents that boost the speed at which the latch circuit operates. See Application at [0028] ("the different supplemental currents provided by PMOS transistors 161 and 162 to the first leg 146 and the second leg 148 of latch circuit 130 may provide a further difference in the total current provided to the differential outputs of latch circuit 130 at nodes 143 and 144. The additional current difference may thus speed up the rate at which the voltages of OUTN and OUTP begin to separate thus improving the speed with which the positive feedback of latch circuit 130 latches").
However, the above arguments are not persuasive because when switch SW1 is on (closed) and the first boost transistor NT31 turns on, then the first boost transistor NT31 will provide the drain-source current of transistor NT31 to node OP which supplement the first drive current of the first leg. Similarly, when switch SW2 is on (closed) and the second boost transistor NT32 turns on, then the second boost transistor NT32 will provide the drain-source current of transistor NT32 to node ON which supplement the second drive current of the second leg. Note that, the for broadest reasonable interpretation, the rejection as discussed above provided items to items matching for the claims limitations including: “a first boost transistor coupled to the first differential amplifier output and configured to provide a first supplemental current to the first differential output of the latch circuit to supplement the first drive current during the active phase,” “a first pass transistor coupled in series with the first boost transistor and configured to block the first supplemental current in response to the latch circuit latching,” “a second boost transistor coupled to the second differential amplifier output and configured to provide a second supplemental current to the second differential output of the latch circuit to supplement the second drive current during the active phase,” and “a second pass transistor coupled in series with the second boost transistor and configured to block the second supplemental current in response to latch circuit latching,”. Thus, for broadest reasonable interpretation, all the limitations of the claims are met as discussed in the rejections above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch, can be reached at (571) 270-8101. The fax number for this group is (571) 273-8300.
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/Long Nguyen/
Primary Examiner
Art Unit 2842