Prosecution Insights
Last updated: October 04, 2026
Application No. 18/667,401

LIGHT-EMITTING DIODE AND LIGHT-EMITTING DEVICE HAVING THE SAME

Non-Final OA §102§103
Filed
May 17, 2024
Priority
Nov 19, 2021 — CIP of PCTCN2021131648
Examiner
HOSSAIN, MOAZZAM
Art Unit
Tech Center
Assignee
Xiamen San'an Optoelectronics Co., Ltd.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
746 granted / 847 resolved
+28.1% vs TC avg
Moderate +11% lift
Without
With
+11.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
45 currently pending
Career history
868
Total Applications
across all art units

Statute-Specific Performance

§101
2.5%
-37.5% vs TC avg
§103
50.4%
+10.4% vs TC avg
§102
25.9%
-14.1% vs TC avg
§112
19.0%
-21.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 847 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election, with traverse, of Species IV. 4th embodiment, figs 5-9 of which claims read upon 1-15 and 17-22 in the “Response to Election / Restriction Filed08/04/2026”, is acknowledged This office action considers claims 1-22 pending for prosecution, of which, non-elected claim 16 is withdrawn, and elected claims 1-15 and 17-22 are examined on their merits. Claim Rejections - 35 USC § 102/103 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (4; Fig 4A; [0039]) = (element 4; Figure No. 4A; Paragraph No. [0038]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above..These conventions are used throughout this document. Claims 1-15 and 17-21 are rejected under 35 U.S.C. 103 as being unpatentable over CHEN; Chao-Hsing et al. (US 20160172560 A1) hereinafter referenced as Chen; in view of SHEN, MING (CN 109728140 A) hereinafter referenced as Shen. or in the alternative are rejected under 35 U.S.C. 103 as being unpatentable over Shen in view of alternative teaching. Regarding claim 1. Chen teaches a light-emitting diode (4; Fig 4A; [0039]) , comprising (see the entire document; Figs. 4a, 4D along with other relevant figures 1At o 6; specifically, as cited below; see alternative rejection of this claim in section II, infra): PNG media_image1.png 397 770 media_image1.png Greyscale Chen Figure 4A Figure 4F, 4L a substrate (425; Fig 4A; [0039]; details depicted in Figs 4B-4L); and a semiconductor layered structure (40; Fig 4L, 4F) located on said substrate, and including at least one light-emitting unit (4 having 45, 46; Figs 4A,4F,4L), an semiconductor island-structure (47, labelled as cushion part; Figs 4A, 4F,4L; [0047]), and a trench (428; Fig 4F; [0045]) that is located between said at least one light-emitting unit (underlying 45.46) and said semiconductor island-structure (47). However, assuming arguendo that the claim must be so narrowly construed such that subject matter of Fig 4F does not expressly anticipate the trench as claimed, then alternatively, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to accommodate the trench of Fig 4F, since this inclusion, at least, in line with the suggestion of MPEP § 2141.02. VI “A prior art reference must be considered in its entirety, i.e., as a whole, W.L. Gore & Associates, Inc. v. Garlock, Inc., 721 F.2d 1540, 220 USPQ 303 (Fed. Cir. 1983), cert. denied, 469 U.S. 851 (1984). Therefore trench pf Fig 4F met the claimed requirement. Furthermore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to look to whole disclosure teaching alternative suitable or useful material or structure of trench, art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP 2144.07. Regarding Claim 2, Chen as applied to the light-emitting diode as claimed in claim 1, further teaches, wherein said trench (428; Fig 4F) has a bottom surface that exposes said semiconductor layered structure (40; Figs 4F,4L). Regarding Claim 3, Chen as applied to the light-emitting diode as claimed in claim 1, further teaches, wherein: said semiconductor layered structure (40; Fig 4L; [0040]) further includes a first semiconductor layer (401), an active layer (402), and a second semiconductor layer (403) that are sequentially stacked (Figs 4B to 4L) from a bottom surface of said semiconductor layered structure; a bottom surface of said trench (428; Fig F) is located below said active layer (402). Regarding Claim 4, Chen as applied to the light-emitting diode as claimed in claim 1, further teaches, wherein a bottom surface of said trench (428; Fig F) is located ([0031]) on said substrate (425). Regarding Claim 5, Chen as applied to the light-emitting diode as claimed in claim 1, further teaches, wherein said semiconductor island-structure ({47,428}, labelled as cushion part; Figs 4A, 4F,4L; [0047])) is located at a geometric center ([0046]) of said light-emitting diode (4). Regarding Claim 6, Chen as applied to the light-emitting diode as claimed in claim 1, does not expressly disclose, wherein an upper surface of said semiconductor island-structure (47) opposite to said substrate (245) has a minimum dimension of at least 30 μm. However, Applicant has not disclosed that having the a minimum dimension of at least 30 μm, i.e., the range of thickmess value, solves any stated problem or is for any particular purpose. On the other hand, Chen establishes in (0047]) a mathematical relationship between the thickness and short circuit probability as “The thickness of the cushion part 47 can be designed to bear the detaching strength of the ejector pin to prevent damages of the light-emitting stack during the ejector pin detaching process. In detail, the cushion part 47 with the designed thickness can prevent short circuits between the first conductive layer 41 and the second conductive layer 43 in the light-emitting element 4 due to the cracks of the first insulating layer 42 occurring in the ejector pin detaching process”, based on the characteristics of 47, from which the thickness of 47 value would be considered result effective variable. Accordingly, the claim is obvious without showing that the claimed range(s) achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious). Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would recognize that it would be obvious to adjust the thickness value in order to adjust the strength value thereof and optimize “ the thickness value [0047]) ” as a "result effective variable”, and arrives at the recited limitation. egarding Claim 7, Chen as applied to the light-emitting diode as claimed in claim 1, further teaches, wherein when viewing said semiconductor island-structure (220) from above said substrate, said semiconductor island-structure (47, labelled as cushion part; Figs 4A,4L; [0047]) has (a circular shape) or a polygonal shape (Fig 4A). Regarding Claim 8, Chen as applied to the light-emitting diode as claimed in claim 1, further teaches, wherein said semiconductor island-structure (47, labelled as cushion part; Figs 4A, 4F,4L; [0047]) has a height that is no greater (depicted in Fig 4F) than a height of said at least one light-emitting unit (4). Regarding Claim 9, Chen as applied to the light-emitting diode as claimed in claim 1, further teaches, (the diode) further comprising a metallic block (construed from [0047]: The material of the cushion part 47 can be metal) disposed on said semiconductor island-structure (47). Regarding Claim 10, Chen as applied to the light-emitting diode as claimed in claim 9, further teaches, wherein said metallic block directly contacts an upper surface of said semiconductor island-structure (construed from [0047]: since, The material of the cushion part 47 can be metal).. Regarding Claim 11, Chen as applied to the light-emitting diode as claimed in claim 9, further teaches, wherein said metallic block (i.e 47) has a thickness that ranges from 0.5 μm to 10 μm. However, Applicant has not disclosed that having a thickness that ranges from 0.5 μm to 10 μm, i.e., the range of thickness value, solves any stated problem or is for any particular purpose. On the other hand, Chen establishes in (0047]) a mathematical relationship between the thickness and short circuit probability as “The thickness of the cushion part 47 can be designed to bear the detaching strength of the ejector pin to prevent damages of the light-emitting stack during the ejector pin detaching process. In detail, the cushion part 47 with the designed thickness can prevent short circuits between the first conductive layer 41 and the second conductive layer 43 in the light-emitting element 4 due to the cracks of the first insulating layer 42 occurring in the ejector pin detaching process”, based on the characteristics of 47, from which the thickness of metallic block 47 value would be considered result effective variable. Accordingly, the claim is obvious without showing that the claimed range(s) achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious). Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would recognize that it would be obvious to adjust the thickness value in order to adjust the strength value thereof and optimize “ the thickness value [0047]) ” as a "result effective variable”, and arrives at the recited limitation. Regarding Claim 12, Chen as applied to the light-emitting diode as claimed in claim 9, further teaches, further comprising a protection layer (44; Fig 4J, 4L; [0048) that covers at least an upper surface and a side wall of said semiconductor island structure (47). Regarding Claim 13, Chen as applied to the light-emitting diode as claimed in claim 12, further teaches, wherein said protection layer (44; Fig 4J, 4L; [0048) has a portion that is located (between said metallic block and said semiconductor island structure) or that is located above said metallic block . Regarding Claim 14, Chen as applied to the light-emitting diode as claimed in claim 12, further teaches, wherein: said light-emitting diode further comprises a first electrode pad (45; Figs 4A, 4L; [0050]) and a second electrode pad (46; Figs 4A, 4L; [0050]); said protection layer (44; Fig 4J, 4L; [0048) covers an upper surface and a side wall of said at least one light-emitting unit; said at least one light-emitting unit includes (Fig 4L; [0040]) a first semiconductor layer (401), an active layer (402), and a second semiconductor layer (403); said first electrode pad (45) is disposed on said protection layer (44) and passes through said protection layer to be electrically connected with said first semiconductor layer (403) of said at least one light-emitting unit; and said second electrode pad (45) is disposed on said protection layer (44; Fig 4J, 4L; [0048) and passes through said protection layer to be electrically connected with said second semiconductor layer (403) of said at least one light-emitting unit. Regarding Claim 15, Chen as applied to the light-emitting diode as claimed in claim 14, further teaches, wherein said first electrode pad (45; Figs 4A, 4L; [0050]) and said second electrode pad (46; Figs 4A, 4L; [0050]) are positioned (depicted in Fig 4L) to prevent said metallic block (47) from being covered. Regarding Claim 17, Chen as applied to the light-emitting diode as claimed in claim 1, further teaches, wherein: said at least one light-emitting unit (4) includes a plurality of light-emitting units (45.46; fig 4A) that are spaced apart from each other. Regarding Claim 18, Chen as applied to the light-emitting diode as claimed in claim 17, further teaches, wherein said semiconductor island-structure (47) is located (Fig 4A, 4L; [0047]) between two adjacent ones (underlying 45,46) of said plurality of light-emitting units. Regarding Claim 19, Chen as applied to the light-emitting diode as claimed in claim 17, further teaches, wherein said semiconductor island-structure (47) is located at a geometric center (Fig 4A, 4L; [0047]) of said light-emitting diode and between two adjacent ones of said plurality of light-emitting units. Regarding Claim 20, Chen as applied to the light-emitting diode as claimed in claim 17, further teaches, wherein two adjacent ones of said plurality of light-emitting units are electrically connected (through 401 depicted in figs 4B-4L). Regarding Claim 21, Chen as applied to the light-emitting diode as claimed in claim 1, further teaches, wherein said trench is tapered (obvious from depression 448’ shape; figs Fig 4L, 5) in a top to bottom direction. Claims 1 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Shen; Ming (CN 109728140 A) hereinafter referenced as Shen ; in view of CHEN; Chao-Hsing et al. (US 20160172560 A1) hereinafter referenced as Chen. Regarding claim 1. Chen teaches a light-emitting diode, comprising (see the entire document; Figs. 4a, 4D along with other relevant figures 1At o 6; specifically, as cited below; see alternative rejection of this claim in section I, supra): PNG media_image2.png 382 1361 media_image2.png Greyscale Shen Figure 1 Figure 6 a substrate (100; Figs 2/6; details depicted in Figs 2-7); and a semiconductor layered structure (stack of {110,120,120}; Figs 2/6) located on said substrate, and including at least one light-emitting unit (L1/L2; Figs 1, 4-7), (see below for “an semiconductor island-structure”), and a trench (30; Fig 1; 310”; fig 6) that is located between said at least one light-emitting unit (underlying L1/L2) and said semiconductor island-structure. But, Shen does not disclose an island structure and trench location defined by island structure. However in the analogous art, as referenced in section I supra, Chen discloses a semiconductor layered structure (40; Fig 4L, 4F) located on said substrate (100), and including at least one light-emitting unit (underlying 45.46; Figs 4A,4F,4L), an semiconductor cushion part (47; Figs 4A, 4F,4L; [0047]), and a trench (428; Fig 4F; [0045]) that is located between said at least one light-emitting unit (underlying 45.46) and said semiconductor island-structure ({47,428}). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to contemplate Shen’s cushion part (47) within Chen’s trench 30, and thereby, the combination of (Shen and Chen)’s light-emitting diode, comprises, inter alia,: “an semiconductor island-structure ( Chen cushion part 47), and a trench (30) that is located between said at least one light-emitting unit (L1/L2) and said semiconductor island-structure ( Chen cushion part 47). The ordinary artisan would have been further motivated to modify Shen in the manner set forth above in order to, at least, prevents Short circuits in the light-emitting element (Chen [0038]). Regarding Claim 22. Shen teaches a light-emitting device (figs 2 to 7) comprising a light-emitting diode as claimed in claim 1 as applied to the light-emitting diode by Shen. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOAZZAM HOSSAIN whose telephone number is (571)270-7960. The examiner can normally be reached M-F: 8:30AM - 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOAZZAM HOSSAIN/Primary Examiner, Art Unit 2898 September 3, 2026
Read full office action

Prosecution Timeline

May 17, 2024
Application Filed
Sep 09, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
99%
With Interview (+11.1%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 847 resolved cases by this examiner. Grant probability derived from career allowance rate.

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