Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6, 10, 13, 21, and 24-27 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Kwon (US 20230128862 A1).
Regarding claim 1, Kwon discloses a semiconductor device (Fig. 9K) comprising: an interconnection line (1133_2); an insulating layer (111_3; para. 108 "Referring to FIG. 9E, in a resultant structure of FIG. 9D, the second redistribution insulating layer 111_2 may be formed on the second redistribution line 1133_2 of the second redistribution pattern 113_2 and the third redistribution insulating layer 111_3", Examiner believes the insulating layers 111_2 and 111_3 to be mistakenly labeled 113_2 and 113_3 respectively on the right edge of the figure) on the interconnection line and having an opening (V2, shown best in Fig. 9E; shown in Fig. 9K as the opening occupied by via 1131_1) exposing a top surface of the interconnection line; and a redistribution pattern (113_1) extending into the opening and electrically connected to the interconnection line at a bottom surface of the opening (Shown, fig. 9E shows that the opening V2 only extends to the upper surface of the interconnection line 113_2), wherein the interconnection line is configured to provide a current path in a first direction (X
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direction along interconnection line) in a region adjacent to the redistribution pattern (Interconnection line and its current path are shown adjacent to redistribution pattern), wherein the opening comprises a first side surface facing the first direction (rightmost sidewall of V2 for example, shown facing the X direction), and wherein a first corner region of the opening protrudes away from or is recessed toward the opening (Fig. 3F, top left corner for example) at a first end portion of the side surface of the opening when viewed in plan view (left end of surface, see attached figure).
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Regarding claim 2, Kwon discloses wherein a second corner region of the opening protrudes away from or is recessed toward the opening at a second end portion of the first side surface of the opening when viewed in plan view (see attached figure).
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Regarding claim 3, Kwon discloses wherein the opening further comprises a second side surface opposite to the first side surface (see attached figure), and wherein the first side surface and the second side surface are symmetrical about an axis extending in the first direction (X direction).
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Regarding claim 4, Kwon discloses wherein a corner region of the opening protrudes away from or is recessed toward the opening at an end portion of the second side surface of the opening when viewed in plan view (see attached figure).
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Regarding claim 5, Kwon discloses wherein the opening further comprises a second side surface opposite to the first side surface, and wherein the first side surface and the second side surface are asymmetrical about an axis extending in a second direction intersecting the first direction (see attached figure).
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Regarding claim 6, Kwon discloses wherein a corner region of the opening does not protrude away from or is not recessed toward the opening at an end portion of the second side surface of the opening when viewed in plan view (see left attached figure; the labeled corner region neither protrudes from nor is recessed toward the opening).
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Regarding claim 10, Kwon discloses wherein the first corner region comprises a stepped shape when viewed in plan view (see attached figure).
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Regarding claim 13, Kwon discloses wherein the opening further comprises a second side surface opposite to the first side surface, and wherein the redistribution pattern on the first side surface and the redistribution pattern on the second side surface are asymmetrical about an axis extending in a second direction intersecting the first direction when viewed in plan view (see attached figure).
Regarding claim 21, Kwon discloses a semiconductor device (Fig. 9K) comprising: an interconnection line (1133_2); an insulating layer (111_3; para. 108 "Referring to FIG. 9E, in a resultant structure of FIG. 9D, the second redistribution insulating layer 111_2 may be formed on the second redistribution line 1133_2 of the second redistribution pattern 113_2 and the third redistribution insulating layer 111_3", Examiner believes the insulating layers 111_2 and 111_3 to be mistakenly labeled 113_2 and 113_3 respectively on the right edge of the figure) on the interconnection line and having an opening (V2, shown best in Fig. 9E; shown in Fig. 9K as the opening occupied by via 1131_1) exposing a top surface of the interconnection line; and a redistribution pattern (113_1) extending into the opening and electrically connected to the interconnection line at a bottom surface of the opening (Shown, fig. 9E shows that the opening V2 only extends to the upper surface of the interconnection line 113_2), wherein the opening comprises a first side surface facing a first direction (rightmost sidewall of
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V2 for example, shown facing the X direction), and a second side surface opposite to the first side surface, and wherein a first portion of the redistribution pattern on the first side surface and a second portion of the redistribution pattern on the second side surface are asymmetrical about an axis extending in a second direction intersecting the first direction when viewed in plan view (see attached figure; Fig. 3F shows opening of redistribution layer shown in Fig. 9K, so the first side surface shown in Fig. 3F is essentially structurally equivalent to the first portion of the redistribution layer).
Regarding claim 24, Kwon discloses wherein the redistribution pattern extends in the first direction when viewed in plan view (Fig. 3F shows at least the opening portion of the redistribution pattern extending in the X direction).
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Regarding claim 26, Kwon discloses a semiconductor device (Fig. 9K) comprising: a semiconductor layer (120) on a substrate (CS); and an interconnection layer (Comprises redistribution insulating layer 111_3, its electrical components, and the layers thereon; Examiner believes Fig. 9K to mistakenly label the insulating layers as 113_3, 113_2, and 113_1 on right side of figure, supported by the description of paragraphs 99-118) on the semiconductor layer, wherein the interconnection layer comprises: a lower insulating layer (111_3, mistakenly labeled 113_3 in Fig. 9K, see para. 99) and a lower interconnection line (1131_2) in the lower insulating layer; an upper interconnection line (1133_2) on the lower interconnection line; an upper insulating layer (111_2, mistakenly labeled 113_2 in Fig. 9K, see para. 108) on the upper interconnection line and having a first opening (V2, shown best in Fig. 9E; shown in Fig. 9F as the opening occupied by via 1131_1) exposing a top surface of the upper interconnection line; a redistribution pattern (113_1) extending into the first opening and electrically connected to the upper interconnection line at a bottom surface of the first opening (Shown); and a passivation layer (111_1, mistakenly labeled 113_1 in Fig. 9K, see para. 113) on the redistribution pattern (Shown) and having a second opening (V3 shown best in Fig. 9H; shown in Fig. 9K as the opening occupied by 115) exposing a top surface of the redistribution pattern (Shown), wherein the upper interconnection line is configured to provide a current path in a first direction (X direction along interconnection line) in a region adjacent to the redistribution pattern (Interconnection line and its current path are shown adjacent to redistribution pattern), wherein the first opening comprises a first side surface facing the first direction (rightmost sidewall of V2 for example, shown facing the X direction), and wherein a corner region (Fig. 3F, top left corner for example) of the first opening protrudes away from or is recessed towards the first opening at an end portion of the first side surface of the first opening when viewed in plan view (see attached figure).
Regarding claim 27, Kwon discloses wherein the semiconductor device comprises a DRAM device (Para. 50 "the semiconductor chip 120 may be a memory chip or a logic chip. The memory chip may be a volatile memory chip such as a dynamic random-access memory (DRAM)").
Claim(s) 1 and 11 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Kwon (US 20230128862 A1).
Regarding claim 1, Kwon discloses a semiconductor device (Fig. 9K) comprising: an interconnection line (1133_2); an insulating layer (111_3; para. 108 "Referring to FIG. 9E, in a resultant structure of FIG. 9D, the second redistribution insulating layer 111_2 may be formed on the second redistribution line 1133_2 of the second redistribution pattern 113_2 and the third redistribution insulating layer 111_3", Examiner believes the insulating layers 111_2 and 111_3 to be mistakenly labeled 113_2 and 113_3 respectively on the right edge of the figure) on the interconnection line and having an opening (V2, shown best in Fig. 9E; shown in Fig. 9K as the opening occupied by via 1131_1) exposing a top surface of the interconnection line; and a redistribution pattern (113_1) extending into the opening and electrically connected to the interconnection line at a bottom surface of the opening (Shown, fig. 9E shows that the opening V2 only extends to the upper surface of the interconnection line 113_2), wherein the interconnection line is configured to provide a current path in a first direction (X direction along interconnection line) in a region adjacent to the redistribution pattern (Interconnection line and its current path are shown adjacent to redistribution pattern), wherein the opening comprises a first side surface facing the first direction (rightmost sidewall of V2 for example, shown facing the X direction), and wherein a first corner region of the opening protrudes away from or is recessed toward the opening (Fig. 3D, top left corner for example) at a first end portion of the side surface of the opening when viewed in plan view (left end of side surface).
Regarding claim 11, Kwon discloses wherein the first corner region comprises a chamfered edge when viewed in plan view (Fig. 3D).
Claim(s) 1 and 12 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Kwon (US 20230128862 A1).
Regarding claim 1, Kwon discloses a semiconductor device (Fig. 9K) comprising: an interconnection line (1133_2); an insulating layer (111_3; para. 108 "Referring to FIG. 9E, in a resultant structure of FIG. 9D, the second redistribution insulating layer 111_2 may be formed on the second redistribution line 1133_2 of the second redistribution pattern 113_2 and the third redistribution insulating layer 111_3", Examiner believes the insulating layers 111_2 and 111_3 to be mistakenly labeled 113_2 and 113_3 respectively on the right edge of the figure) on the interconnection line and having an opening (V2, shown best in Fig. 9E; shown in Fig. 9K as the opening occupied by via 1131_1) exposing a top surface of the interconnection line; and a redistribution pattern (113_1) extending into the opening and electrically connected to the interconnection line at a bottom surface of the opening (Shown, fig. 9E shows that the opening V2 only extends to the upper surface of the interconnection line 113_2), wherein the interconnection line is configured to provide a current path in a first direction (X direction along interconnection line) in a region adjacent to the redistribution pattern (Interconnection line and its current path are shown adjacent to redistribution pattern), wherein the opening comprises a first side surface facing the first direction (rightmost sidewall of V2 for example, shown facing the X direction), and wherein a first corner region of the opening protrudes away from or is recessed toward the opening (Fig. 3C, top left corner for example) at a first end portion of the side surface of the opening when viewed in plan view (left end of side surface).
Regarding claim 12, Kwon discloses wherein the first corner region comprises a curved surface that is convex toward an outside of the opening when viewed in plan view (Fig. 3C).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon (US 20230128862 A1).
Regarding claim 8, Kwon discloses the semiconductor device of claim 1, wherein a minimum thickness of the redistribution pattern on the first side surface ranges from about 1.01 μm to about 23 μm when viewed in cross-sectional view (Fig. 9K shows redistribution pattern 113_1 comprising 113_1S and 113_1M; para. 44 "a thickness of each of the first seed layer 113_1S… may range from about 0.01 µm to about 3 µm, and a thickness of each of the first metal layer 113_1M… may range from about 1 μm to about 20 μm", Kwon therefore teaches a redistribution pattern having a minimum thickness of 1.01 µm). Nonetheless, it would have been obvious to one of ordinary skill in the art prior to the effective time of filing to modify Kwon such that a minimum thickness of the distribution pattern on the first side surface would instead range from about 0.1 µm to about 0.5 µm in order to save space for better routing density and maintain lower material costs by forming thinner interconnects, as is common in the field of memory devices. Furthermore, “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, F.2d 454, 456, 105 USPQ 223, 235 (CCPA 1955).
Allowable Subject Matter
Claims 7, 9, 14 and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 7, the prior art of record does not disclose the device of claim 1 wherein the opening further comprises a second side surface opposite to the first side surface, wherein the first corner region protrudes in a second direction intersecting the first direction, and wherein a width of the first corner region in the first direction ranges from about 1% to about 40% of a distance between the first side surface and the second side surface in the first direction. Specifically, the prior art fails to disclose wherein a width of the first corner region in the first direction ranges from about 1% to about 40% of a distance between the first side surface and the second side surface in the first direction.
Regarding claim 9, the prior art of record does not disclose the device of claim 1 wherein the opening further comprises a second side surface opposite to the first side surface, and wherein a first thickness of a first portion of the redistribution pattern on the first side surface is substantially equal to or greater than a second thickness of a second portion of the redistribution pattern on the second side surface when viewed in plan view. Specifically, the prior art of record fails to disclose wherein a first thickness of a first portion of the redistribution pattern on the first side surface is substantially equal to or greater than a second thickness of a second portion of the redistribution pattern on the second side surface when viewed in plan view.
Regarding claim 14, the prior art of record does not disclose the device of claim 1 wherein the redistribution pattern comprises a recess on the bottom surface of the opening, and wherein the recess has an asymmetrical shape with respect to an axis extending perpendicular to the first direction when viewed in plan view.
Regarding claim 23, the prior art of record does not disclose the device of claim 21 wherein a first thickness of the first portion of the redistribution pattern on the first side surface is greater than a second thickness of the second portion of the redistribution pattern on the second side surface when viewed in cross-sectional view.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL J SMITH whose telephone number is (703)756-5706. The examiner can normally be reached M-F 8-5 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571) 272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S.J.S./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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