DETAILED ACTION
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4-7, 9, 11-15 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Bertin et al. (US 6396121 B1, hereinafter Bertin’121) in view of Kim et al. (US 20240088015 A1, hereinafter Kim’015).
Regarding independent claim 1, Bertin’121 teaches, “A semiconductor device (fig. 1-10, related descriptions) comprising:
an antifuse structure (fig. 5-6, fig. 10) comprising a plurality of spaced apart antifuse vias (‘a plurality of anti-fuses’, column 4, line 18. Capacitor comprising elements 34, 36, 42 and 72 shown in figs. 3D, 4, 5A, 6, 7 are antifuse vias) having a first portion embedded in a shallow trench isolation structure (40) and a second portion embedded in a middle-of-the-line (MOL) dielectric layer (38),
each of the antifuse vias having a first end and a second end that is opposite the first end, a frontside metal line of a frontside back-end-of-the-line (BEOL) structure (contact 42 in fig. 5A, ‘GC’ in fig. 10) connected (electrically) to the first end of each of the antifuse vias, and a backside power distribution network metal line connected (electrically) to the second end of each of the antifuse vias (‘a connection to the bulk silicon layer is made on the back side of the chip’, fig. 6, lines 28-30, Bulk silicon layer is one electrode of the capacitor)”.
But Bertin’121 is silent upon the provision of wherein the semiconductor device comprising a frontside metal line and a backside power distribution network metal line.
However, Kim’015 teaches a similar memory device (fig. 1A-1B), wherein capacitor (antifuse) (1C/UC) has one electrode (20b) connected to a frontside metal line (Mx1) of a frontside back-end-of-the-line (BEOL) structure (PDN1a) and the other electrode (20a) is connected to a backside power distribution network metal line (Dx1, PDN2a).
Bertin’121 and Kim’015 are analogous art because they both are directed to semiconductor memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Bertin’121 with the features of Kim’015 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Bertin’121 and Kim’015 to include front side and backside power rail according to the teachings of Kim’015 with a general motivation of achieving reduced power transmission loss by lowering frontside routing congestion.
Regarding claims 4, Bertin’121 modified with Kim’015 further teaches, “The semiconductor device of Claim 1, wherein the frontside metal line (Mx1, fig. 1A, Kim’015) is connected to the first end of each of the antifuse vias (1C) by frontside metal vias (18b, 22a)”.
Regarding claim 5, Bertin’121 modified with Kim’015 further teaches, “The semiconductor device of Claim 4, wherein the frontside metal vias (18b, fig. 1A, Kim’015) are embedded in a frontside interlayer dielectric (ILD) (16b) and each frontside metal via lands on the MOL dielectric layer (38, fig. 3D, Bertin’121)”.
Regarding claim 6, Bertin’121 modified with Kim’015 further teaches, “The semiconductor device of Claim 1, wherein the backside power distribution network metal line (Dx1, fig. 1A, Kim’015) is connected to the second end of each of the antifuse vias (1C) by backside power rails (PDN2a)”.
Regarding claim 7, Bertin’121 modified with Kim’015 further teaches, “The semiconductor device of Claim 6, wherein the backside power rails embedded in a backside ILD layer (embedding conductive elements e.g., power rail in ILD is conventional in semiconductor chip), and each backside power rail (Dx1, fig. 1A, Kim’015) lands on (‘ON’ is a broad limitataion) a surface of the shallow trench dielectric structure (40, fig. 4, Bertin’121)”.
Regarding independent claim 9, Bertin’121 teaches, “A semiconductor device (fig. 1-10, related descriptions) comprising:
an antifuse structure (fig. 5-6, fig. 10) comprising a plurality of spaced apart non-electrically conductive antifuse vias (‘a plurality of anti-fuses’, column 4, line 18. Capacitor comprising elements 34, 36, 42 and 72 shown in figs. 3D, 4, 5A, 6, 7 are antifuse vias, before breakdown of the capacitor dielectric 34, the antifuses are non-electrically conductive) having a first portion embedded in a shallow trench isolation structure (40) and a second portion embedded in a MOL dielectric layer (38),
each of the non-electrically conductive antifuse vias having a first end and a second end that is opposite the first end, a frontside metal line of a frontside BEOL structure (contact 42 in fig. 5A, ‘GC’ in fig. 10) connected to the first end of each of the non-electrically conductive antifuse vias, and
a backside power distribution network metal line connected to the second end of each of the non-electrically conductive antifuse vias (‘a connection to the bulk silicon layer is made on the back side of the chip’, fig. 6, lines 28-30)”.
But Bertin’121 is silent upon the provision of wherein the semiconductor device comprising a frontside metal line and a backside power distribution network metal line.
However, Kim’015 teaches a similar memory device (fig. 1A-1B), wherein capacitor (antifuse) (1C/UC) has one electrode (20b) connected to a frontside metal line (Mx1) of a frontside back-end-of-the-line (BEOL) structure (PDN1a) and the other electrode (20a) is connected to a backside power distribution network metal line (Dx1, PDN2a).
Bertin’121 and Kim’015 are analogous art because they both are directed to semiconductor memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Bertin’121 with the features of Kim’015 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Bertin’121 and Kim’015 to include front side and backside power rail according to the teachings of Kim’015 with a general motivation of achieving reduced power transmission loss by lowering frontside routing congestion.
Regarding claims 11, Bertin’121 modified with Kim’015 further teaches, “The semiconductor device of Claim 9, wherein the frontside metal line (Mx1, fig. 1A, Kim’015) is connected to the first end of each of the non-electrically conductive antifuse vias (1C) by frontside metal vias (18b, 22a)”.
Regarding claim 12, Bertin’121 modified with Kim’015 further teaches, “The semiconductor device of Claim 11, wherein the frontside metal vias (18b, fig. 1A, Kim’015) are embedded in a frontside interlayer dielectric (ILD) (16b) and each frontside metal via lands on the MOL dielectric layer (38, fig. 3D, Bertin’121)”.
Regarding claim 13, Bertin’121 modified with Kim’015 further teaches, “The semiconductor device of Claim 9, wherein the backside power distribution network metal line (Dx1, fig. 1A, Kim’015) is connected to the second end of each of the non-electrically conductive vias (1C) by backside power rails (PDN2a)”.
Regarding claim 14, Bertin’121 modified with Kim’015 further teaches, “The semiconductor device of Claim 13, wherein the backside power rails embedded in a backside ILD layer (embedding conductive elements e.g., power rail in ILD is conventional in semiconductor chip), and each backside power rail (Dx1, fig. 1A, Kim’015) lands on (‘ON’ is a broad limitataion) a surface of the shallow trench dielectric structure (40, fig. 4, Bertin’121)”.
Regarding independent claim 15, Bertin’121 teaches, “A semiconductor device (fig. 1-10, related descriptions) comprising:
an antifuse structure (fig. 5-6, fig. 10) comprising a plurality of spaced apart electrically conductive antifuse vias (‘a plurality of anti-fuses’, column 4, line 18. Capacitor comprising elements 34, 36, 42 and 72 shown in figs. 3D, 4, 5A, 6, 7 are antifuse vias. Antifuse vias become electrically conductive ‘by applying a voltage sufficient to cause breakdown of the capacitor dielectric 34’, column 5, lines 47-48) having a first portion embedded in a shallow trench isolation structure (40) and a second portion embedded in a MOL dielectric layer (38),
each of the electrically conductive antifuse vias having a first end and a second end that is opposite the first end, a frontside metal line of a frontside BEOL structure contact 42 in fig. 5A, ‘GC’ in fig. 10) electrically connected to the first end of each of the electrically conductive antifuse vias, and a backside power distribution network metal line electrically connected to the second end of each of the electrically conductive antifuse vias (‘a connection to the bulk silicon layer is made on the back side of the chip’, fig. 6, lines 28-30)”.
But Bertin’121 is silent upon the provision of wherein the semiconductor device comprising a frontside metal line and a backside power distribution network metal line.
However, Kim’015 teaches a similar memory device (fig. 1A-1B), wherein capacitor (antifuse) (1C/UC) has one electrode (20b) connected to a frontside metal line (Mx1) of a frontside back-end-of-the-line (BEOL) structure (PDN1a) and the other electrode (20a) is connected to a backside power distribution network metal line (Dx1, PDN2a).
Bertin’121 and Kim’015 are analogous art because they both are directed to semiconductor memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Bertin’121 with the features of Kim’015 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Bertin’121 and Kim’015 to include front side and backside power rail according to the teachings of Kim’015 with a general motivation of achieving reduced power transmission loss by lowering frontside routing congestion.
Regarding claim 17, Bertin’121 modified with Kim’015 further teaches, “The semiconductor device of Claim 15, wherein the frontside metal line (Mx1, fig. 1A, Kim’015) is electrically connected to the first end of each of the electrically conductive antifuse vias by frontside metal vias (Mx1, fig. 1A, Kim’015)”.
Regarding claim 18, Bertin’121 modified with Kim’015 further teaches, “The semiconductor device of Claim 17, wherein the frontside metal vias (18b, fig. 1A, Kim’015) are embedded in a frontside interlayer dielectric (ILD) (16b) and each frontside metal via lands on the MOL dielectric layer (38, fig. 3D, Bertin’121)”.
Regarding claim 19, Bertin’121 modified with Kim’015 further teaches, “The 19. The semiconductor device of Claim 15, wherein the backside power distribution network metal line (Dx1, fig. 1A, Kim’015) is electrically connected to the second end of each of the electrically conductive vias (1C) by backside power rails (PDN2a)”.
Regarding claim 20, Bertin’121 modified with Kim’015 further teaches, “The semiconductor device of Claim 19, wherein the backside power rails embedded in a backside ILD layer (embedding conductive elements e.g., power rail in ILD is conventional in semiconductor chip), and each backside power rail (Dx1, fig. 1A, Kim’015) lands on (‘ON’ is a broad limitataion) a surface of the shallow trench dielectric structure (40, fig. 4, Bertin’121)”.
Claims 2-3, 10 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Bertin’121 Kim’015 as applied to claims 1, 9 and 15 as above, and further in view of Johns (US 20020168801 A1, hereinafter Johns’801).
Regarding claim 2, Bertin’121 modified with Kim’015 teaches all the limitations described in claim 1.
But Bertin’121 modified with Kim’015 is silent upon the provision of wherein each of the antifuse vias is composed of a material that in an initial stage is not electrically conductive, but upon application of energy, the material becomes conductive.
However, Johns’801 teaches a similar antifuse vias composed of a material (16, amorphous silicon, fig. 6) that in an initial stage is not electrically conductive, but upon application of energy, the material becomes conductive (fig. 6).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Bertin’121 modified with Kim’015 and Johns’801 to use amorphous silicon as antifuse material according to the teachings of Johns’801 as ‘The result is an antifuse that is well isolated from other wiring and a standard via that will facilitate good electrical contact between metal layer 1 and 2’. See Johns’801, ABSTRACT.
Regarding claim 3, Bertin’121 modified with Kim’015 further teaches, “The semiconductor device of Claim 2, wherein the material of the antifuse vias (15, fig. 6) comprises amorphous polysilicon, a phase change material or a Si-based dielectric containing a dopant (amorphous polysilicon)”.
Regarding claim 10, Bertin’121 modified with Kim’015 further teaches, “The semiconductor device of Claim 9, wherein the non-electrically conductive antifuse vias (15, fig. 6) are composed of amorphous polysilicon, a phase change material or a Si-based dielectric containing a dopant (amorphous polysilicon)”.
Regarding claim 16, Bertin’121 modified with Kim’015 further teaches, “The semiconductor device of Claim 15, wherein the electrically conductive antifuse vias are composed of crystalline silicon, a phase change material or a Si-based dielectric containing a dopant (amorphous polysilicon is a phase change material)”.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Bertin’121 Kim’015 as applied to claim 1 as above, and further in view of Liao et al. (US 20250089229 A1, hereinafter Liao’229).
Regarding claim 8, Bertin’121 modified with Kim’015 teaches all the limitations described in claim 1.
Bertin’121 further teaches, wherein the semiconductor device of Claim 1, further comprising at least one transistor (fig. 10, DRAM transistors comprising gates GC etc.) located adjacent to the antifuse structure,
But Bertin’121 modified with Kim’015 is silent upon the provision of wherein the at least one transistor is electrically connected to another frontside metal line of the BEOL structure.
However, Liao’229 teaches a similar device (fig. 4), wherein the at least one transistor is electrically connected to another frontside metal line (M5) of the BEOL structure.
Bertin’121 modified with Kim’015 and Liao’229 are analogous art because they both are directed to semiconductor memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Bertin’121 modified with Kim’015 with the features of Liao’229 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Bertin’121 modified with Kim’015 and Liao’229 to connect the transistor frontside metal line of the BEOL structure according to the teachings of Liao’229 as this is conventional and essential element.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
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