DETAILED ACTION
Notice of Pre-AIA or AIA Status
Applicant’s amendment, filed 04/20/2026, for application number 18/667,614 has been received and entered into record. Claims 1-8, 11, 12, 14, 15, 18 and 20 are amended. Thus, claims 1-20 are presented for examination.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6, 8-10, 15-17 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Perelygin et al. (US 11,080,111 B1).
Regarding claim 1, Perelygin teaches one or more processors (Figures 1-5, CPUs and GPUs 110, Figures 12, 38), comprising: circuitry to:
determine that one or more software programs are to share information between two or more threads (“cooperating threads can refer to a plurality of threads including instructions to perform a task and that exchange data through shared memory.” Col. 45, ll. 52-55 and “threads 306 in a thread block or CTA 304 communicate and synchronize with other threads 306 in a thread block or CTA 304.” Col. 6, ll. 62-64 and Figure 3, kernel 308); and
cause the one or more software programs to be modified to cause a first-to-begin thread of the two or more threads to initialize one or more portions of memory to be used by the two or more threads to share the information (“individual CTAs or CGs 610 contain threads, each containing run-time instructions for a kernel 606.” Col. 10, ll. 25-27 and “one or more patches 612 are a set of instructions inserted by a compiler 604 into a kernel 606 that, when executed, perform operations related to resource preemption during execution on one or more GPUs.” Col. 10, ll. 37-41 and “a lock 622 checks if a location in shared memory is set to a specific value prior to execution of a body 614 of run-time instructions 610 in a kernel 606 … if a location in shared memory is not set to a specific value, a lock 622 will set said location to said specific value and a body 614 of run-time instructions 610 for a kernel 606 are executed.” col. 10, ll. 63-67 and col. 11, ll. 1-2 and “an initialization routine 608 is a set of instructions that, when executed, prepare a kernel 606 for execution on a [GPU] by setting initial data values and performing any other operations necessary to setup a kernel 606 for execution.” Col. 10, ll. 9-13 and Figures 6, 7) [the compiler modifies software by inserting patches (that include initialization routines and lock logic) to identify a first thread (first-to-begin thread) to reach a shared memory location to set initial values and setup the execution environment].
Claims 8 and 15 correspond to claim 1 and are rejected accordingly.
Regarding claim 2, Perelygin teaches the one or more processors of claim 1, wherein the circuitry is to modify the one or more software programs at runtime of the one or more software programs (“device kernel driver 2706 may be configured to compile intermediate representation (“IR”) code into binary code at runtime.” Col. 52, ll. 21-23 and “Source code may be compiled … online during execution of an application” col. 54, ll. 65-67 and Figure 27) [the circuitry performs compilation and modification of the kernels into their binary form (executable) during runtime].
Claims 9 and 16 correspond to claim 2 and are rejected accordingly.
Regarding claim 3, Perelygin teaches the one or more processors of claim 1, wherein the modification comprises selecting one or more instructions with which to perform the initialization (“a compiler 604 links in supporting libraries implementing additional functionality such as parallel computing functionality provided by an API… during compilation of a kernel 606.” Col. 9, ll. 42-46 and column 10 and Figure 6) [the compiler modifies software by selecting a set of instructions (initialization routine) to set the program’s initial data values].
Claims 10 and 17 correspond to claim 3 and are rejected accordingly.
Regarding claim 6, Perelygin teaches the one or more processors of claim 1, wherein the information is to be initialized on a reserved shared memory included in one or more GPUs (“shared memory on a GPU is a group of circuits to store data values that are used by one or more thread blocks” col. 7, ll. 33-35 and “acquire resources required to execute a kernel 606 or an individual CTA or CG 610 and, when enough resources have been acquired, set an indication in shared memory that a specific kernel 606 has begun execution.” Col. 11, ll. 11-15 and column 10 and Figure 4) [the GPU shared memory stores data values set by initialization routine once the execution resources are acquired (reserved)].
Claim 19 corresponds to claim 6 and is rejected accordingly.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 5, 7, 11-14, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Perelygin in view of Levit-Gurevich (US 2023/0109752 A1).
Regarding claim 4, Perelygin teaches the one or more processors of claim 1. However, Perelygin does not explicitly teach wherein the one or more software programs comprise one or more GPU kernels, and the modification comprises inserting one or more instructions to be performed by the one or more GPU kernels to perform the initialization prior to each of one or more invocations of one or more APIs within the one or more software programs.
In the analogous art, Levit-Gurevich teaches wherein the one or more software programs comprise one or more GPU kernels (“As used herein, a GPU kernel refers to a kernel in binary format.” Par 0042), and the modification comprises inserting one or more instructions to be performed by the one or more GPU kernels to perform the initialization prior to each of one or more invocations of one or more APIs within the one or more software programs (“the profiling instructions 104A-104C are inserted at a first address (e.g., a first position) of a kernel (e.g., the beginning of the first kernel 106) to initialize variables used for profiling.” Par 0069 and “the trace emulator 430 can execute the first instrumentation routine 1302 prior to executing the emulation routine (EmulRoutines) and the second instrumentation routine 1304 after executing the emulation routine.” Par 0170 and paragraphs 99-102 and Figure 12) [this shows inserting instructions (which perform initialization) at beginning of kernel (prior to execution calls)].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Perelygin and Levit-Gurevich before him before the effective filing date of the claimed invention, to have modified Perelygin to incorporate the teachings of Levit-Gurevich to insert instructions for the GPU kernels to perform before the API invocations to execute emulation routines to generate and provide data to a GPU profiling tool which can identify improvements to GPU/CPU operations. (Levit-Gurevich, paragraph 99)
Claims 11 and 18 correspond to claim 4 and are rejected accordingly.
Regarding claim 5, Perelygin teaches the one or more processors of claim 1, However, Perelygin does not explicitly teach wherein the one or more software programs comprise one or more GPU kernels, and the modification comprises inserting one or more instructions to be performed by the one or more GPU kernels after each of one or more invocations of one or more APIs within the one or more software programs.
In the analogous art, Levit-Gurevich teaches wherein the one or more software programs comprise one or more GPU kernels (“As used herein, a GPU kernel refers to a kernel in binary format.” Par 0042), and the modification comprises inserting one or more instructions to be performed by the one or more GPU kernels after each of one or more invocations of one or more APIs within the one or more software programs (“insert a second callback routine in the instrumented routine after the emulation routine, the second call-back routine to invoke the first API or a second API to provide the first GPU state to the application.” Par 0305 and “In some examples, in response to executing the second instrumentation routine 1304, the trace emulator 430 can invoke a callback routine (e.g., “CallbackAfter( )”) to invoke an API to provide GPU states of the hardware thread that executed the software thread to an upper level construct, such as the application 120 of FIG. 1 , the hardware profiling analysis tool 718 of FIG. 7 , etc.” par 0172).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Perelygin and Levit-Gurevich before him before the effective filing date of the claimed invention, to have modified Perelygin to incorporate the teachings of Levit-Gurevich to insert instructions for the GPU kernels to perform after each of the API invocations to provide GPU states of the head thread prior to and after executing the emulation routine to determine changes in the GPU states and generate profiling data and determine appropriate improvements to be made. (Levit-Gurevich, paragraph 172)
Claim 12 corresponds to claim 5 and is rejected accordingly.
Regarding claim 7, Perelygin teaches the one or more processors of claim 1. However, Perelygin does not explicitly teach wherein the one or more software programs comprise one or more GPU kernels, and the modification comprises inserting one or more instructions to be performed by the first-to-begin thread of the one or more GPU kernels.
In the analogous art, Levit-Gurevich teaches wherein the one or more software programs comprise one or more GPU kernels (“As used herein, a GPU kernel refers to a kernel in binary format.” Par 0042), and the modification comprises inserting one or more instructions to be performed by the first-to-begin thread of the one or more GPU kernels (“the thread dispatcher 506 may load initial GPU state(s) into an idle one of the thread(s) 208 and start its execution based on the determination(s).” par 0120 and “Identified Events may include, but are not limited to: (a) Code dispatch” par 0224 and “the profiling instructions 104A-104C are inserted at a first address (e.g., a first position) of a kernel (e.g., the beginning of the first kernel 106)” par 0069 and “Specifically, a process is to save data before the first instruction (ADD) of the code (code dispatch point),” par 0239 and Figure 2) [the code dispatch point marks the start of kernel execution; instructions are inserted before kernel’s main execution by hardware thread (first-to-begin thread)].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Perelygin and Levit-Gurevich before him before the effective filing date of the claimed invention, to have modified Perelygin to incorporate the teachings of Levit-Gurevich to insert instructions by the first-to-begin thread to allow for the execution environments to be initialized with initial data values and be ready for program execution.
Claims 14 and 20 correspond to claim 7 and are rejected accordingly.
Regarding claim 13, Perelygin teaches the one or more processors of claim 8. However, Perelygin does not explicitly teach wherein the information is to be initialized on a memory that is not accessible until performance of a GPU kernel thread of one or more software programs associated with the memory has started.
In the analogous art, Levit-Gurevich teaches wherein the information is to be initialized on a memory that is not accessible until performance of a GPU kernel thread of one or more software programs associated with the memory has started (“As used herein, a GPU state refers to one or more first values stored in a general-purpose register file (GRF) and/or one or more second values stored in an architecture register file (ARF) associated with a hardware thread of the GPU.” Par 0045 and “the thread dispatcher 506 may load initial GPU state(s) into an idle one of the thread(s) 208 and start its execution based on the determination(s).” par 0120 and Figure 5) [this shows initial GPU states, stored in thread specific registers, are only loaded into the thread and execution is started synchronously by the dispatcher, meaning those register contents only become relevant/accessible to the executing thread right at the beginning of its performance].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Perelygin and Levit-Gurevich before him before the effective filing date of the claimed invention, to have modified Perelygin to incorporate the teachings of Levit-Gurevich to forestall access to the information to be initialized on a memory before the GPU kernel thread performance has started to prevent a program to access or alter memory areas, ensuring system stability and security.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 8 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
No additional arguments were presented as to the remaining claims. As such, the rejection is maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AYMAN FATIMA whose telephone number is (571)270-0830. The examiner can normally be reached M to Fri EST.
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/AYMAN FATIMA/Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176
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