Office Action Predictor
Last updated: April 16, 2026
Application No. 18/667,629

CIRCUIT BOARD

Non-Final OA §102
Filed
May 17, 2024
Examiner
NORRIS, JEREMY C
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electro-Mechanics Co., LTD.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
89%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
840 granted / 973 resolved
+18.3% vs TC avg
Minimal +3% lift
Without
With
+2.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
23 currently pending
Career history
996
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
40.6%
+0.6% vs TC avg
§102
53.2%
+13.2% vs TC avg
§112
4.6%
-35.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 973 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2018/0027646 A1 (Sumida). Sumida discloses, referring primarily to figure 1, a circuit board (24), comprising: a substrate portion comprising at least one circuit wire ([0037]); an adhesive layer (31) disposed on a first side of the substrate portion; and a metal reinforcing layer (34) disposed opposite to the substrate portion with respect to the adhesive layer, wherein the metal reinforcing layer comprises a first surface which has a convex portion (35) , and a second surface disposed opposite to the first surface [claim 1], wherein the second surface of the metal reinforcing layer has a recess portion (37) [claim 2], wherein a position of the convex portion of the first surface of the metal reinforcing layer and a position of the recess portion of the second surface of the metal reinforcing layer correspond to each other (figure 1) [claim 3], wherein the convex portion is disposed in a quantity of at least two (figure 1) [claim 4], wherein the first surface of the metal reinforcing layer contacts a first surface of the adhesive layer (figure 1) [claim 5], wherein the first surface of the adhesive layer has a recess portion (31A) that corresponds to the convex portion of the first surface of the metal reinforcing layer [claim 6], wherein the convex portion of the metal reinforcing layer has a dome shape (figure 1) [claim 7], wherein the convex portion of the metal reinforcing layer has a rectangular pillar shape [claim 8], wherein the substrate portion comprises: a first protective layer disposed on a first surface of the adhesive layer; a first connection pad disposed in the first protective layer; a first insulation layer disposed on the first protective layer; and a first circuit wire disposed in the first insulation layer ([0037]) [claim 9], wherein the substrate portion further comprises a first via layer disposed in the first insulation layer and connected to the first circuit wire ([0037]-[0039]) [claim 10], wherein the substrate portion further comprises a cavity (29A, 29B), and at least a portion of the cavity (29A) is disposed in the first insulation layer [claim 11], wherein the cavity extends to the first protective layer [claim 12], wherein the substrate portion comprises: a core layer (27) disposed opposite to the metal reinforcing layer with respect to the adhesive layer; a first insulation layer disposed between the adhesive layer and the core layer; a second insulation layer disposed opposite to the first insulation layer with respect to the core layer; a first circuit wire disposed in the first insulation layer; and a second circuit wire disposed in the second insulation layer ([0037]-[0039]) [claim 13], wherein the substrate portion further comprises: a first connection pad disposed opposite to the core layer with respect to the first insulation layer, and disposed on a surface of the first insulation layer; and a second connection pad disposed opposite to the core layer with respect to the second insulation layer, and disposed on a surface of the second insulation layer ([0037]-[0039]) [claim 14], wherein the substrate portion further comprises: a first via layer (29A) disposed in the first insulation layer; and a second via layer (29B) disposed in the second insulation layer [claim 15], wherein the substrate portion further comprises: a first protective layer disposed opposite to the core layer with respect to the first insulation layer, and disposed to embed at least a portion of the first connection pad; and a second protective layer disposed opposite to the core layer with respect to the second insulation layer, and disposed to embed at least a portion of the second connection pad [claim 16]. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEREMY C NORRIS whose telephone number is (571)272-1932. The examiner can normally be reached 7:15-15:15 M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571)272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. JEREMY C. NORRIS Examiner Art Unit 2847 /JEREMY C NORRIS/Primary Examiner, Art Unit 2847
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Prosecution Timeline

May 17, 2024
Application Filed
Feb 21, 2026
Non-Final Rejection — §102
Apr 06, 2026
Response Filed

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604416
LAMINATE FOR WIRING BOARD
2y 5m to grant Granted Apr 14, 2026
Patent 12598703
WIRING CIRCUIT BOARD
2y 5m to grant Granted Apr 07, 2026
Patent 12598698
WIRING CIRCUIT BOARD
2y 5m to grant Granted Apr 07, 2026
Patent 12598693
THICK FILM PRINTED COOLER FOR IMPROVED THERMAL MANAGEMENT OF DIRECT BONDED POWER DEVICES
2y 5m to grant Granted Apr 07, 2026
Patent 12593395
WIRING BOARD AND METHOD FOR MANUFACTURING WIRING BOARD
2y 5m to grant Granted Mar 31, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
89%
With Interview (+2.6%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 973 resolved cases by this examiner. Grant probability derived from career allow rate.

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