DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This OA is in response to the claims filled on 5/17/2024 that has been entered, wherein claims 1-20 are pending and claim 20 is withdrawn.
Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-19 in the reply filed on 7/21/2026 is acknowledged. Claim 20 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/17/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9, 11-14 and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ji et al. (US 2015/0130075 A1).
Regarding claim 1, Ji teaches a semiconductor package(Fig. 14) comprising:
a package body comprising:
a connection member(20, ¶0081) having a first surface and a second surface opposite the first surface; and
at least one semiconductor chip(40, ¶0081) on the first surface of the connection member(20, ¶0081);
a connection terminal(29, ¶0059) on the second surface of the connection member(20, ¶0081), and connected to the at least one semiconductor chip(40, ¶0081) through the connection member(20, ¶0081); and
at least one magnet(11, 13, 12, 21, 23, 22, 24, 26, 25, 41, 43, 42, ¶0082) in the package body, the at least one magnet(11, 13, 12, 21, 23, 22, 24, 26, 25, 41, 43, 42, ¶0082) arranged to correspond to a warpage profile(¶0075, ¶0089) of the package body.
The limitation of “at least one magnet(11, 13, 12, 21, 23, 22, 24, 26, 25, 41, 43, 42, ¶0082) configured to correct warpage of the package body by applying a force to the package body in response to an external magnetic field applied to the semiconductor package” is a recitation how the product/device is being used. The structure as defined in Ji could be used in the manner claimed (i.e. the at least one magnet of Ji could be configured to correct warpage of the package body by applying a force to the package body in response to an external magnetic field applied to the semiconductor package) and thus Ji anticipates the limitations of this claim. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim, MPEP 2114 (II).
Regarding claim 2, Ji teaches the semiconductor package of claim 1, wherein the package body comprises a first portion(please see examiner annotated Fig. 7) having a first warpage along a first direction and a second portion(please see examiner annotated Fig. 7) having a second warpage along a second direction different from the first direction,
wherein the at least one magnet(11, 13, 12, 21, 23, 22, 24, 26, 25, 41, 43, 42, ¶0082) comprises a first magnet(23, ¶0063) in the first portion of the package body and a second magnet(21, ¶0063) in the second portion of the package body, wherein the first magnet(23, ¶0063) has a first magnetic pole orientation(N-pole, Fig. 3, ¶0063), and
wherein the second magnet(21, ¶0063) has a second magnetic pole orientation(S-pole, Fig. 3, ¶0064) different from the first magnetic pole orientation(N-pole, Fig. 3, ¶0063).
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Regarding claim 3, Ji teaches the semiconductor package of claim 2.
The limitation of “the first magnet(23, ¶0063) is configured to apply a first force to the first portion of the package body in response to the external magnetic field being applied to the semiconductor package, the first force having a direction substantially opposite to the first direction, and wherein the second magnet(21, ¶0063) is configured to apply a second force to the second portion of the package body in response to the external magnetic field being applied to the semiconductor package, the second force having a direction substantially opposite to the second direction” is a recitation how the product/device is being used. The structure as defined in Ji could be used in the manner claimed (i.e. the first magnet of Ji could be configured to apply a first force to the first portion of the package body in response to the external magnetic field being applied to the semiconductor package, the first force having a direction substantially opposite to the first direction and the second magnet of Ji could be to configured to apply a second force to the second portion of the package body in response to the external magnetic field being applied to the semiconductor package, the second force having a direction substantially opposite to the second direction) and thus Ji anticipates the limitations of this claim. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim, MPEP 2114 (II).
Regarding claim 4, Ji teaches the semiconductor package of claim 2, wherein at least one of the first magnet(23, ¶0063) and the second magnet(21, ¶0063) comprises a plurality of portions spaced apart from each other(Fig. 14).
Regarding claim 5, Ji teaches the semiconductor package of claim 2, wherein the warpage profile of at least one of the first portion and the second portion is wave-shaped(please see examiner annotated Fig. 7).
Regarding claim 6, Ji teaches the semiconductor package of claim 1.
Regarding the limitation of “based on the warpage of the package body occurring when the semiconductor package undergoes a reflow soldering, at least one magnet(11, 13, 12, 21, 23, 22, 24, 26, 25, 41, 43, 42, ¶0082) is configured to apply the force to the package body in response to the external magnetic field being applied to the semiconductor package during the reflow soldering”, Ji shows all aspects of the semiconductor device according to the instant invention, and that the step of based on the warpage of the package body occurring when the semiconductor package undergoes a reflow soldering, at least one magnet(11, 13, 12, 21, 23, 22, 24, 26, 25, 41, 43, 42, ¶0082) is configured to apply the force to the package body in response to the external magnetic field being applied to the semiconductor package during the reflow soldering, are considered to be process limitations that does not affect the structure of the final device. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. See MPEP 2113.1
Regarding claim 7, Ji teaches the semiconductor package of claim 6, wherein the at least one magnet(11, 13, 12, 21, 23, 22, 24, 26, 25, 41, 43, 42, ¶0082) has a ferromagnetism(¶0059).
Regarding the limitation of “the at least one magnet(11, 13, 12, 21, 23, 22, 24, 26, 25, 41, 43, 42, ¶0082) is further configured to maintain the ferromagnetism during the reflow soldering”, Ji shows all aspects of the semiconductor device according to the instant invention, and that the step of “the at least one magnet(11, 13, 12, 21, 23, 22, 24, 26, 25, 41, 43, 42, ¶0082) is further configured to maintain the ferromagnetism during the reflow soldering”, are considered to be process limitations that does not affect the structure of the final device. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. See MPEP 2113.1
Regarding claim 8, Ji teaches the semiconductor package of claim 1, wherein the connection member(20, ¶0081) comprises a package substrate(¶0059) or a redistribution layer, and wherein the at least one magnet(11, 13, 12, 21, 23, 22, 24, 26, 25, 41, 43, 42, ¶0082) is embedded in the connection member(20, ¶0081) or is disposed on the first surface and the second surface of the connection member(20, ¶0081).
Regarding claim 9, Ji teaches the semiconductor package of claim 1, wherein the at least one semiconductor chip(40, ¶0081) is connected to the connection member(20, ¶0081) by a bonding-wire method or a flip-chip method(Fig. 14).
Regarding claim 11, Ji teaches a semiconductor package(Fig. 14), comprising:
a package body comprising:
a connection member(20, ¶0081) having a first surface and a second surface; and
at least one semiconductor chip(40, ¶0081) on the first surface of the connection member(20, ¶0081);
at least one first magnet(23, ¶0063); and
at least one second magnet(21, 24, ¶0063) spaced apart from the at least one first magnet(23, ¶0063),
The limitation of “in response to an external magnetic field being applied to the package body, the at least one first magnet(23, ¶0063) is configured to apply a first force to the package body in a first direction, and the at least one second magnet(21, ¶0063) is configured to apply a second force to the package body in a second direction that is different from the first direction” is a recitation how the product/device is being used. The structure as defined in Ji could be used in the manner claimed (i.e. the at least one first magnet of Ji could be configured to apply a first force to the package body in a first direction and the at least one second magnet of Ji, configured to apply a second force to the package body in a second direction that is different from the first direction) and thus Ji anticipates the limitations of this claim. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim, MPEP 2114 (II).
Regarding claim 12, Ji teaches the semiconductor package of claim 11, wherein the at least one first magnet(23, ¶0063) and the at least one second magnet(21, ¶0063) are embedded(¶0077) within the connection member(20, ¶0081).
Regarding claim 13, Ji teaches the semiconductor package of claim 11, wherein the at least one first magnet(23, ¶0063) is provided on the second surface of the connection member(20, ¶0081), and
wherein the at least one second magnet(24, ¶0063) is provided on the first surface of the connection member(20, ¶0081) and is spaced apart from the at least one semiconductor chip(40, ¶0081).
Regarding claim 14, Ji teaches the semiconductor package of claim 11, wherein the package body comprises:
a first portion(please see examiner annotated Fig. 7) within which the at least one semiconductor chip(40, ¶0081) is provided and that warps downward, and
a second portion(please see examiner annotated Fig. 7) that warps downward.
The limitation of “a first portion(please see examiner annotated Fig. 7) that warps downward in response to heat being applied to the package body, and
a second portion(please see examiner annotated Fig. 7) that warps downward in response to heat being applied to the package body,
wherein the first force applied by the at least one first magnet(23, ¶0063) is configured to correct the upward warpage of the first portion, and
wherein the second force applied by the at least one second magnet(21, ¶0063) is configured to correct the downward warpage of the second portion” is a recitation how the product/device is being used. The structure as defined in Ji could be used in the manner claimed (i.e. the first portion of Ji could be configured warps downward in response to heat being applied to the package body, and the second portion of Ji, configured warps downward in response to heat being applied to the package body and the at least one first magnet of Ji could be configured to apply a first force to correct the upward warpage of the first portion and the at least one second magnet of Ji, configured to apply a second force to correct the downward warpage of the second portion) and thus Ji anticipates the limitations of this claim. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim, MPEP 2114 (II).
Regarding claim 16, Ji teaches the semiconductor package of claim 11, wherein the at least one first magnet(23, ¶0063) is provided within a perimeter defined by the at least one semiconductor chip(40, ¶0081).
Regarding claim 17, Ji teaches the semiconductor package of claim 16, wherein the at least one second magnet(21, ¶0063) is provided outside of the perimeter defined by the at least one semiconductor chip(40, ¶0081).
Regarding claim 18, Ji teaches the semiconductor package of claim 11, further comprising a plurality of connection terminals(29, ¶0059) on the second surface of the connection member(20, ¶0081), wherein the at least one first magnet(23, ¶0063) and the at least one second magnet(21, ¶0063) are provided so as to not vertically overlap with the plurality of connection terminals(29, ¶0059).
Regarding claim 19, Ji teaches the semiconductor package of claim 11, further comprising a plurality of connection terminals(29, ¶0059) on the second surface of the connection member(20, ¶0081),
wherein the at least one first magnet(23, ¶0063) is provided between the plurality of connection terminals(29, ¶0059).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Ji et al. (US 2015/0130075 A1).
Regarding claim 10, Ji teaches the semiconductor package of claim 1.
The embodiment of Fig. 14 of Ji is not relied on to teach a mold layer on the first surface of the connection member(20, ¶0081) and encapsulating at least a portion of the at least one semiconductor chip(40, ¶0081).
The embodiment of Fig. 16 of Ji teaches a semiconductor package(Fig. 16) comprising mold layer(18, ¶0086) on the first surface of the connection member(70, ¶0085) and encapsulating at least a portion of the at least one semiconductor chip(80, ¶0085). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of embodiment of Fig. 14 to include mold layer on the first surface of the connection member and encapsulating at least a portion of the at least one semiconductor chip, as taught by the embodiment of Fig. 16 in order to project the package from contaminates in the external environment.
Allowable Subject Matter
Claim 15 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Regarding dependent claim 15, the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach “a lowermost layer of the plurality of layers is an insulating layer, and wherein the at least one first magnet and the at least one second magnet are embedded in the insulating layer”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Pietambaram et al. (US 2020/0005987 A1) Discloses a semiconductor package.
Ishii et al. (US 2023/0298955 A1) Discloses a semiconductor package.
Siko et al. (US 2024/0071863 A1) Discloses a semiconductor package.
Hsu et al. (US 2024/0215174 A1) Discloses a semiconductor package.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA DYKES whose telephone number is (571)270-3161. The examiner can normally be reached M-F 9:30 am-5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAURA M DYKES/Examiner, Art Unit 2892
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