Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 and 7-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20220013502 A1), hereinafter referred to as “Lee502”, in view of Chuang et al. (US 20230245987 A1) hereinafter referred to as “Chuang987”.
Regarding claim 1: Lee502 teaches a semiconductor package (abstract) comprising: a first semiconductor chip (See at least Fig 3., element 10C); and a second semiconductor chip (See at least Fig. 3, element 20C) hybrid-bonded to the first semiconductor chip (“The first semiconductor chip 10C and the second semiconductor chip 20C may be attached to each other through a metal-oxide hybrid bonding”, para. [0027]), wherein the first semiconductor chip comprises a plurality of first main pads (See Fig. 3 annotated below) and a first bonding insulation layer extending around the plurality of first main pads (See at least Fig. 4, element 10UI), wherein the plurality of first main pads are spaced apart from each other (See at least Fig. 2), wherein the second semiconductor chip comprises a plurality of second main pads (See Fig. 3 annotated below) and a second bonding insulation layer (See at least Fig. 4, element 20UI) extending around the plurality of second main pads, wherein the plurality of second main pads are spaced apart from each other (See at least Fig. 2), and wherein the plurality of second main pads are aligned with the plurality of first main pads (See Fig 3. Annotated below, first main pads and second main pads are shown to be aligned and flush with each other, this is also shown in at least Fig. 2), and wherein the second bonding insulation layer is bonded to the first bonding insulation layer (“The first semiconductor chip 10C and the second semiconductor chip 20C may be attached to each other through a metal-oxide hybrid bonding by the first main connection pad structure MP1, the dummy connection pad structure DP, the first bonding insulating layer 10UI, and the second bonding insulating layer 20UI.”, para. [0027]).
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Close up view of the Main pad region (MPR1) shown in Fig. 3 of Lee502 and annotated: First main pads are spaced apart from each other and aligned with second main pads which are also spaced apart from each other.
Lee502 does not teach that each of the plurality of first main pads comprises a plurality of first sub main pads spaced apart from each other, wherein each of the plurality of second main pads comprises a plurality of second sub main pads spaced apart from each other, wherein each of the plurality of second sub main pads is bonded to a respective one of the plurality of first sub main pads.
Chuang987 teaches a slotted bond pad structure where a main bond pad is split up into a plurality of sub-main bond pads (See Fig. 7B annotated below, “The bond pad comprises interior sidewalls defining one or more cavities that are surrounded by the bond pad. The one or more cavities are filled with a dielectric material of the dielectric structure, so that a top surface of the bond pad comprises a plurality of discrete top surface segments that are laterally separated from one another by the dielectric structure, as viewed in a cross-sectional view. Because the dielectric material is disposed directly between the plurality of discrete top surface segments, a polishing pad used to form the bond pad will have a relatively small overlap with individual ones of the top surface segments. The relatively small overlap reduces dishing of the individual top surface segments. The reduced dishing decreases formation of voids when bond pads of separate integrated chip die are brought together, thereby improving an electrical performance and/or a reliability of a multi-dimensional integrated chip structure.”, para [0022]).
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Fig. 7B taken from Chuang987 and annotated: Main bond pad (Element 112 inside black dashed line) is divided into four sub-main bond pads at the corners (SMB with large black arrows).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the main bond pads in the device disclosed in Lee502 with the slotted bond pad structure disclosed in Chuang987, motivated by the teachings of Chuang987, to improve the electrical performance and/or reliability of the multi-dimensional integrated chip structure disclosed in Lee502, thereby arriving at the claimed invention. Such a modification could be performed with a reasonable expectation of success.
Regarding claim 2: Lee502 teaches that the top surface of each of the plurality of first main pads is coplanar with a top surface of the first bonding insulation layer, and wherein a bottom surface of each of the plurality of second main pads is coplanar with a bottom surface of the second bonding insulation layer (“A top surface of each first connection pad 16 may be arranged coplanar with a top surface of the first bonding insulating layer 10UI, and a top surface of each second connection pad 26 may be arranged coplanar with a top surface of the second bonding insulating layer 20UI”, para. [0053]).
Regarding claim 3: Lee502 teaches that the first main bond pads (See Fig. 3 annotated above) and second main bond pads (See Fig. 3 annotated above) are surrounded by an insulating layer (See at least Fig. 3, insulating layers 10UI and 20UI).
Lee502 does not teach that the first bonding insulation layer is between the plurality of first sub main pads, and the second bonding insulation layer is between the plurality of second sub main pads.
Chuang987 teaches that a dielectric material surrounds the sub-main bond pads (“The dielectric structure 104 is disposed within the one or more cavities 113 and directly between the plurality of discrete top surface segments”, para. [0026], see Fig. 7B annotated above, the cross shape dividing the main bond pad into sub-main bond pads (SMB) is a dielectric material).
Using the same reasoning that was used to reject claim 1, modifying the device disclosed in Lee502 by changing the bond pad structure to that disclosed in Chuang987 would result in the claimed invention, since the sub-main bond pads would be surrounded by the insulating layers, (See at least Fig. 3 in Lee502, elements 10UI and 20UI). Such a modification could be performed with a reasonable expectation of success.
Regarding claim 4: Lee502 does not teach that each of the plurality of first main pads is divided by the first bonding insulation layer into the plurality of first sub main pads, and each of the plurality of second main pads is divided by the second bonding insulation layer into the plurality of second sub main pads.
Chuang 987 teaches the that each of the plurality of first main pads is divided by the first bonding insulation layer into the plurality of first sub main pads, and each of the plurality of second main pads is divided by the second bonding insulation layer into the plurality of second sub main pads. (See Fig. 7B annotated above, each of the sub-main bond pads (SMB) are surrounded by the dielectric material layer, element 104).
Using the same reasoning that was used to reject claim 1, modifying the device disclosed in Lee502 by changing the bond pad structure to that disclosed in Chuang987 would result in the claimed invention, since the sub-main bond pads would be surrounded by the insulating layers, see at least Fig. 3 in Lee502, elements 10UI and 20UI). Such a modification could be performed with a reasonable expectation of success.
Regarding claim 5: Lee502 teaches that each of the first bonding insulation layer and the second bonding insulation layer comprises a silicon oxide layer or a silicon nitride layer (“In example embodiments, the first bonding layer 18B and the second bonding layer 28B may include silicon oxide”, para. [0057]).
Regarding claim 7: Lee 502 does not teach that a width of each of the plurality of second sub main pads is equal to a width of each of the plurality of first sub main pads.
Chuang987 teaches that a plurality of second sub main pads may be equal to a width of each of the plurality of first sub main pads. (The width of the bond pad segments in regions 116 and 218 appear to be substantially the same in all figures).
Using the same reasoning that was used to reject claim 1, modifying the device disclosed in Lee502 by changing the bond pad structure to that disclosed in Chuang987 would result in the claimed invention, since the first sub-main bond pads and second sub-main bond pads would have the same width. Such a modification could be performed with a reasonable expectation of success.
Regarding claim 8: Lee502 does not teach that each of the plurality of second sub main pads is bonded to a respective one of the plurality of first sub main pads at a respective bonding region, and wherein the second bonding insulation layer is bonded to the first bonding insulation layer at an insulating bonding region.
Chuang987 teaches that each of the plurality of second sub main pads is bonded to a respective one of the plurality of first sub main pads at a respective bonding region, and wherein the second bonding insulation layer is bonded to the first bonding insulation layer at an insulating bonding region. (“The first IC die 202 is bonded to the second IC die 208 along a hybrid bonding interface, in which the bond pad 112 contacts the additional bond pad 218 along a conductive interface and the dielectric structure 104 contacts the additional dielectric structure 210 along a dielectric interface.”, para. [0034], As understood by the examiner, having separate bonding regions for the first sub-main pads, second sub-main pads and the bonding insulation layers is the process known as hybrid bonding).
Using the same reasoning that was used to reject claim 1, modifying the device disclosed in Lee502 by changing the bond pad structure to that disclosed in Chuang987 would result in the claimed invention, since the same hybrid bonding process is also used in Lee502 (“The first semiconductor chip 10C and the second semiconductor chip 20C may be attached to each other through a metal-oxide hybrid bonding”, para. [0027]). Such a modification could be performed with a reasonable expectation of success.
Regarding claim 9: Lee502 teaches that the plurality of first main pads (See at least Fig. 4, element 26) are in a first main pad region (See Fig. 2, element MPR1) located in a central region of the first semiconductor chip in a plan view (See Fig. 2), and the plurality of second main pads (See at least Fig. 4 element 16) are in a second main pad region (Also MPR1) located in a central region of the second semiconductor chip in the plan view (As understood by the examiner, the first main pads and second main pads as defined in the instant case are overlapping each other, and as shown in Figs. 9-11 in the specification, overlap with each other in a one-to-one ratio. Therefore, the first main pads and second main pads exist in the same region in a plan view.)
Regarding claim 10: Lee502 teaches that the first semiconductor chip further comprises a first dummy pad region (See Fig. 2, element DPR) in a peripheral region that extends around the first main pad region (See Fig. 2, DPR regions completely surround the MPR1 region in the plan view), wherein the first dummy pad region comprises first dummy pads (See Fig. 5 taken from Lee502 annotated below) arranged therein, and wherein the second semiconductor chip further comprises a second dummy pad region (As understood by the examiner, in the instant case, the first dummy pads belonging to the first semiconductor chip and the second dummy pads belonging to the second semiconductor chip are overlapping and therefore occupy the same region in a plan view) in a peripheral region that extends around the second main pad region (See Fig. 2, element DPR, dummy pad region completely surrounds main pad region MPR1).
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Fig 5. Taken from Lee502 and annotated: First and second main pads indicated by black arrows, first and second dummy pads indicated by red arrows.
Regarding claim 11: Lee502 teaches a semiconductor package (abstract) comprising: a first semiconductor chip (See at least Fig 3., element 10C); and a second semiconductor chip (See at least Fig. 3, element 20C) hybrid-bonded to the first semiconductor chip (“The first semiconductor chip 10C and the second semiconductor chip 20C may be attached to each other through a metal-oxide hybrid bonding”, para. [0027]), wherein the first semiconductor chip comprises a plurality of first main pads (See Fig. 3 annotated above), a first bonding insulation layer extending around the plurality of first main pads (See at least Fig. 4, element 10UI), and a support pad (In light of the specification and using the broadest reasonable interpretation, a support pad is considered to be any structure made of a conductive material that connected to the main pad, such as the wiring layers shown in Lee502 Fig. 12, elements 118B, 128B, 138B), wherein the plurality of first main pads are spaced apart from each other (See at least Fig. 2), wherein the second semiconductor chip comprises a plurality of second main pads (See Fig. 3 annotated above) and a second bonding insulation layer extending around the plurality of second main pads (See at least Fig. 4, element 20UI), wherein the plurality of second main pads are spaced apart from each other (See at least Fig. 2), wherein the second semiconductor chip further comprises a support via (Fig. 12, elements 118A, 128A, 138A), and wherein the second bonding insulation layer is bonded to the first bonding insulation layer (“hybrid bonding”, para. [0027]).
Lee502 does not teach wherein each of the plurality of first main pads comprises a plurality of first sub main pads spaced apart from each other, and wherein the plurality of first sub main pads are on the support pad, wherein each of the plurality of second main pads comprises a plurality of second sub main pads spaced apart from each other and wherein the plurality of second sub main pads are on the support via, wherein each of the plurality of second sub main pads is bonded to a respective one of the plurality of first sub main pads.
Chuang987 teaches a slotted bond pad structure where a main bond pad is split up into a plurality of sub-main bond pads (See Fig. 7B annotated above, “The bond pad comprises interior sidewalls defining one or more cavities that are surrounded by the bond pad. The one or more cavities are filled with a dielectric material of the dielectric structure, so that a top surface of the bond pad comprises a plurality of discrete top surface segments that are laterally separated from one another by the dielectric structure, as viewed in a cross-sectional view. Because the dielectric material is disposed directly between the plurality of discrete top surface segments, a polishing pad used to form the bond pad will have a relatively small overlap with individual ones of the top surface segments. The relatively small overlap reduces dishing of the individual top surface segments. The reduced dishing decreases formation of voids when bond pads of separate integrated chip die are brought together, thereby improving an electrical performance and/or a reliability of a multi-dimensional integrated chip structure.”, para [0022]).
Using the same reasoning that was used to reject claim 1, modifying the device disclosed in Lee502 by changing the bond pad structure to that disclosed in Chuang987 would result in the claimed invention, since the first sub-main bond pads and second sub-main bond pads would be on the support pad and the support via (Here “on” is interpreted by the examiner to mean that the structures do not have to be in direct contact, but that the first sub-main bond pads and second sub-main bond pads are above the support pad and support via in the semiconductor device stack). Such a modification could be performed with a reasonable expectation of success.
Regarding claim 12: Lee502 teaches that the support pad is spaced apart from the first bonding insulation layer (In light of the specification, see at least Fig. 2, the support pad is in contact with the first bonding insulation layer 10UI, therefore the examiner interprets “spaced apart” to mean that the support pad is not within the first bonding insulation layer, therefore, as seen in Fig. 12 of Lee502, elements 118B, 128B, 138B serve as the support pads which are spaced apart from bonding insulating layers 122D and 132D).
Lee502 does not teach that the first bonding insulation layer is between the plurality of first sub main pads.
Chuang987 teaches that a dielectric material surrounds the sub-main bond pads (“The dielectric structure 104 is disposed within the one or more cavities 113 and directly between the plurality of discrete top surface segments”, para. [0026], see Fig. 7B annotated above, the cross shape dividing the main bond pad into sub-main bond pads (SMB) is a dielectric material).
Using the same reasoning that was used to reject claim 1 and claim 3, modifying the device disclosed in Lee502 by changing the bond pad structure to that disclosed in Chuang987 would result in the claimed invention, since the sub-main bond pads would be surrounded by the insulating layers, (See at least Fig. 3 in Lee502, elements 10UI and 20UI). Such a modification could be performed with a reasonable expectation of success.
Regarding claim 13: Lee502 does not teach that the second bonding insulation layer is between the plurality of second sub main pads, and wherein the support via is on the second bonding insulation layer and the plurality of second sub main pads.
Chuang 987 teaches the that each of the plurality of first main pads is divided by the first bonding insulation layer into the plurality of first sub main pads, and each of the plurality of second main pads is divided by the second bonding insulation layer into the plurality of second sub main pads. (See Fig. 7B annotated above, each of the sub-main bond pads (SMB) are surrounded by the dielectric material layer, element 104).
Using the same reasoning that was used to reject claim 1, modifying the device disclosed in Lee502 by changing the bond pad structure to that disclosed in Chuang987 would result in the claimed invention, since the sub-main bond pads would be surrounded by the insulating layers, (See at least Fig. 3 in Lee502, elements 10UI and 20UI). Additionally, the second sub-main pads would be on the support via (See Fig. 12 in Lee502, bond pads 126MP above via 118A). Such a modification could be performed with a reasonable expectation of success.
Regarding claim 14: Lee502 teaches that a width of the support pad is greater than a width of each of the plurality of first main pads. (See close up of Fig. 12 annotated below, the support pad 118B is depicted as being substantially wider that main pads 126MP).
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Close up of Fig 12 in Lee502 with annotations: In the illustrations disclosed in Lee502, the support pad (wiring layer 118 B) is shown to be substantially wider than the first and second main pads (126 MP). The support via (through via 118 A) is shown to be substantially the same width as the main pads (126 MP).
Regarding claim 15: Lee502 does not teach that a width of the support via is greater than a width of each of the plurality of second sub main pads.
Chuang 987 teaches the that each of the plurality of first main pads is divided by the first bonding insulation layer into the plurality of first sub main pads, and each of the plurality of second main pads is divided by the second bonding insulation layer into the plurality of second sub main pads. (See Fig. 7B annotated above, each of the sub-main bond pads (SMB) are surrounded by the dielectric material layer, element 104).
Using the same reasoning that was used to reject claim 1, modifying the device disclosed in Lee502 by changing the bond pad structure to that disclosed in Chuang987 would result in the claimed invention, since the first and second sub-main bond pads would have a width smaller than the support via (See Fig. 12 in Lee502, the bond pads 126MP as depicted have substantially the same width as the support vias 118A, therefore if the bond pad structure 126MP was changed as taught by Chuang987 then the resulting sub-main bond pads would have a smaller width). Such a modification could be performed with a reasonable expectation of success.
Regarding claim 16: A semiconductor package comprising: a first semiconductor chip (See at least Fig. 3, element 10C); and a second semiconductor chip (See at least Fig. 3, element 20C) hybrid-bonded to the first semiconductor chip (“The first semiconductor chip 10C and the second semiconductor chip 20C may be attached to each other through a metal-oxide hybrid bonding”, para. [0027]), wherein the first semiconductor chip comprises a first substrate structure (See at least Fig. 3, element 10W), a plurality of first main pads on the first substrate structure (See Fig. 3 annotated above), and a first bonding insulation structure extending around the plurality of first main pads (See at least Fig. 3, element 10UI), wherein the first substrate structure comprises a support pad (See Fig. 12, at least element 118B), and wherein the plurality of first main pads are spaced apart from each other (See at least Fig. 2), wherein the second semiconductor chip comprises a second substrate structure (See at least Fig. 3, element 20W), a plurality of second main pads spaced apart from each other (See at least Fig. 2), and a second bonding insulation structure extending around the plurality of second main pads (See at least Fig. 3, element 20UI), and wherein the second substrate structure comprises a support via (See Fig. 12, at least element 118A), and wherein the second bonding insulation structure is bonded to the first bonding insulation structure (“hybrid bonding”, para. [0027]).
Lee502 does not teach that each of the plurality of first main pads comprises a plurality of first sub main pads spaced apart from each other, and wherein the plurality of first sub main pads are supported by the support pad, wherein each of the plurality of second main pads includes a plurality of second sub main pads spaced apart from each other, wherein the plurality of second sub main pads are supported by the support via, wherein each of the plurality of second sub main pads is bonded to a respective one of the plurality of first sub main pads.
Chuang 987 teaches the that each of the plurality of first main pads is divided by the first bonding insulation layer into the plurality of first sub main pads, and each of the plurality of second main pads is divided by the second bonding insulation layer into the plurality of second sub main pads. (See Fig. 7B annotated above, each of the sub-main bond pads (SMB) are surrounded by the dielectric material layer, element 104).
Using the same reasoning that was used to reject claim 1, modifying the device disclosed in Lee502 by changing the bond pad structure to that disclosed in Chuang987 would result in the claimed invention, since the first and second sub-main bond pads would be supported by the support via (Using the broadest reasonable interpretation of “supported by” the vias in Fig. 12 of Lee502, such as element 118A, are considered to be supporting every pair of bond pads above it in the semiconductor device stack). Such a modification could be performed with a reasonable expectation of success.
Regarding claim 17: Lee502 teaches that the first substrate structure further comprises a wiring layer (Fig. 12, element 118B), and wherein the support pad is in the wiring layer and supports each of the plurality of first main pads (In light of the specification, the examiner interprets the support pad as being part of the wiring layer or the wiring layer itself).
Regarding claim 18: Lee502 teaches that the second substrate structure further comprises a silicon layer (“The first substrate 10W and the second substrate 20W may be formed based as a Group IV material wafer such as a silicon wafer”, para. [0047]), and wherein the support via supports each of the plurality of second main pads (As explained in rejecting claim 17, any support via such as Fig. 12, element 118A is considered by the examiner to be supporting every pair of bond pads above it).
Regarding claim 19: Lee502 teaches that the first bonding insulation structure (10UI) comprises a plurality of insulating layers, and wherein the second bonding insulation structure (20UI) comprises a plurality of insulating layers (See Fig. 4, “In example embodiments, the first bonding layer 18B and the second bonding layer 28B may include silicon oxide, silicon carbon nitride (SiCN), or the like. The first bonding layer 18B and the second bonding layer 28B may be bonded by applying a high-temperature annealing operation when the first bonding layer 18B and the second bonding layer 28B are in contact with each other. The first insulating layer 18A and the second insulating layer 28A may include silicon oxide. For example, the first insulating layer 18A and the second insulating layer 28A may include at least one of tetraethyl orthosilicate (TEOS), Tonen SilaZene (TOSZ), atomic layer deposition (ALD) oxide, flowable chemical vapor deposition (FCVD) oxide, high density plasma (HDP) oxide, plasma enhanced oxidation (PEOX) oxide, but are not limited thereto”, para. [0057]).
Regarding claim 20: Lee502 teaches that a width of the support pad is greater than a width of each of the plurality of first main pads. (Fig. 12, element 118B is depicted as having substantially greater width than the bond pads 126MP).
Lee502 does not teach that a width of the support via is greater than a width of each of the plurality of second sub main pads.
Chuang 987 teaches the that each of the plurality of first main pads is divided by the first bonding insulation layer into the plurality of first sub main pads, and each of the plurality of second main pads is divided by the second bonding insulation layer into the plurality of second sub main pads. (See Fig. 7B annotated above, each of the sub-main bond pads (SMB) are surrounded by the dielectric material layer, element 104).
Using the same reasoning that was used to reject claim 1, modifying the device disclosed in Lee502 by changing the bond pad structure to that disclosed in Chuang987 would result in the claimed invention, since the first and second sub-main bond pads would have a width smaller than the support via (See Fig. 12 in Lee502, the bond pads 126MP as depicted have substantially the same width as the support vias 118A, therefore if the bond pad structure 126MP was changed as taught by Chuang987 then the resulting sub-main bond pads would have a smaller width). Such a modification could be performed with a reasonable expectation of success.
Claim 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20220013502 A1), hereinafter referred to as “Lee502”, in view of Chuang et al. (US 20230245987 A1) hereinafter referred to as “Chuang987” and Chen et al. (US 20210057363 A1), hereinafter referred to as “Chen363”.
Regarding claim 6: In addition to the reasoning used to reject claim 1, Lee502 does not explicitly teach that a thickness of each of the plurality of second sub main pads is less than a thickness of each of the plurality of first sub main pads.
Chen363 recognizes that the thickness of a bond pad structure can affect the electrical resistance of the semiconductor device (“By reducing the thickness of the surface dielectric layer 126, the height of the bonding pads 128 may be reduced, which can reduce the resistance of the bonding pads 128 and improve electrical performance of the device.”, para. [0034]). Therefore, the thickness of the bond pads is a result-effective variable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the result-effective variable of the first sub-main bond pad thickness in order to determine the optimum or workable ranges and arrive at the claimed invention (MPEP 2144.05). Furthermore, the applicant has not presented persuasive evidence that the claimed thickness is for a particular purpose that is critical to the overall claimed invention.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered relevant to the Applicant’s Disclosure: Wang et al. (US 20220302056 A1) and Li et al. (US 20240055401 A1) teach multiple bond pads and insulation layers hybrid-bonded together, where multiple bond pad pairs are connected to the same wiring structures and vias.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT L STEWART whose telephone number is (571)-270-0853. The examiner can normally be reached M-F 8:00am-4:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571)-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ROBERT L STEWART/ Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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