DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 20 is objected to because of the following informalities: the third line from the last should read “wherein each of the conductive connection members…”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 11 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen’364 (US 2020/0303364).
Regarding claim 11, Chen’364 discloses, in FIG. 1G and in related text, a semiconductor package, comprising:
a lower package (BPU) having a first planar area and opposite first and second lower package sides that extend in a first direction (vertical direction in FIG. 1G);
an upper package (700A) stacked on the lower package by conductive connection members (760), the upper package having a second planar area smaller than the first planar area, the upper package having opposite first and second upper package sides that extend in the first direction, wherein a center of the lower package is offset relative to a center of the upper package, thereby defining an underfill region (between 700A and 700B) on an upper surface of the lower package between the second upper package side (right side of upper package 700A) and the second lower package side (right side of lower package BPU); and
an underfill member (800) extending from the underfill region on the upper surface of the lower package to fill a space between the lower package and the upper package (see Chen’384, [0024], [0028]-[0029]).
Regarding claim 13, Chen’364 discloses the structure of claim 11.
Chen’364 discloses wherein the underfill member (800) comprises a first extension portion that covers at least a portion of the second upper package side (right side) of the upper package (700A) (see Chen’364, FIG. 1G).
Claims 11 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen’996 (US 2022/0084996).
Regarding claim 11, Chen’996 discloses, in FIG. 16 and in related text, a semiconductor package, comprising:
a lower package (300, 400, 500, 600) having a first planar area and opposite first and second lower package sides that extend in a first direction (vertical direction in FIG. 16);
an upper package (110) stacked on the lower package by conductive connection members (contact bumps), the upper package having a second planar area smaller than the first planar area, the upper package having opposite first and second upper package sides that extend in the first direction, wherein a center of the lower package is offset relative to a center of the upper package, thereby defining an underfill region (to the right of upper package 110) on an upper surface of the lower package between the second upper package side (right side of upper package 110) and the second lower package side (right side of lower package 300, 400, 500, 600); and
an underfill member (130) extending from the underfill region on the upper surface of the lower package to fill a space between the lower package and the upper package (see Chen’996, [0049], [0052], [0060], [0064]).
Regarding claim 13, Chen’996 discloses the package of claim 11.
Chen’996 discloses wherein the underfill member (130) comprises a first extension portion that covers at least a portion of the second upper package side (right side) of the upper package (110) (see Chen’996, FIG. 16).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Chen’364.
Regarding claim 14, Chen’364 discloses the structure of claim 11.
Chen’364 discloses wherein the second upper package side (right side of upper package 700A) is spaced apart from the second lower package side by at least 0 mm, or by the size of chip 710B (see Chen’364, FIG. 1G, [0028]).
Chen’364 does not explicitly disclose wherein the second upper package side is spaced apart from the second lower package side by at least 0.5 mm.
However, it is well known that the size of a chip is proportional to its complexity (see, for example, Brent et al., The chip complexity of binary arithmetic, STOC '80: Proceedings of the twelfth annual ACM symposium on Theory of computing, Pages 190 – 200). In other words, the limitation (or the size of chip 710B) is a result effective variable for varying. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to have the claimed range/value through routine experimentation and optimization. Also, applicant has not disclosed that the claimed range is for a particular unobvious purpose, produces an unexpected result, or otherwise critical. See MPEP § 2144.05.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chen’996 in view of Hilton (US 2002/0060084).
Regarding claim 15, Chen’996 discloses the structure of claim 11.
Chen’996 does not explicitly disclose wherein the lower package comprises a dam structure that extends along the second lower package side within the underfill region on the upper surface of the lower package and has a predetermined height from the upper surface of the lower package.
Hilton teaches wherein the lower package (130) comprises a dam structure (240) that extends along the second lower package side within the underfill region (to the right side of 110) on the upper surface of the lower package and has a predetermined height (H) from the upper surface of the lower package (see Hilton, FIG. 2A, [0023]-[0025]).
Chen’996 and Hilton are analogous art because they both are directed to semiconductor packaging and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chen’996with the features of Hilton because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Chen’996 to include wherein the lower package comprises a dam structure that extends along the second lower package side within the underfill region on the upper surface of the lower package and has a predetermined height from the upper surface of the lower package, as taught by Hilton, to prevent creation of stress concentration (see Hilton, [0025]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Chen’996 in view of Hilton (US 2002/0060084).
Regarding claim 16, Chen’996 discloses the structure of claim 11.
Chen’996 does not explicitly disclose wherein the lower package comprises a receiving groove that extends along the second lower package side within the underfill region on the upper surface of the lower package and has a predetermined depth below the upper surface of the lower package.
Hilton teaches wherein the lower package (430) comprises a receiving groove that extends along the second lower package side within the underfill region (to the right of 110) on the upper surface of the lower package and has a predetermined depth (H) below the upper surface of the lower package (see Hilton, FIG. 4, [0031]-[0032]).
Chen’996 and Hilton are analogous art because they both are directed to semiconductor packaging and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chen’996with the features of Hilton because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Chen’996 to include wherein the lower package comprises a receiving groove that extends along the second lower package side within the underfill region on the upper surface of the lower package and has a predetermined depth below the upper surface of the lower package, as taught by Hilton, to reduce stress concentration (see Hilton, [0033]).
Allowable Subject Matter
Claims 1-10 are allowed.
Claims 12 and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 20 would be allowable if rewritten or amended to overcome the objection(s), set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, Chen’996, discloses a semiconductor package, comprising: a lower package having opposite first and second lower package sides that extend in a first direction; an upper package stacked on the lower package by conductive connection members, the upper package having opposite first and second upper package sides that extend in the first direction, and the second upper package side is spaced apart from the second lower package side by a predetermined distance to define an underfill region on an upper surface of the lower package; an underfill member extending from the underfill region on the upper surface of the lower package to fill a space between the lower package and the upper package. The prior art of records, individually or in combination, do not disclose nor teach “wherein the first upper package side and the first lower package side are co-planar” in combination with other limitations as recited in claim 1.
The prior art of records, individually or in combination, do not disclose nor teach “wherein the first upper package side and the first lower package side are co-planar” in combination with other limitations as recited in claim 12.
The prior art of record, Chen’364, discloses wherein the lower package has opposite third and fourth lower package sides that extend in a second direction transverse to the first direction, wherein the upper package has opposite third and fourth upper package sides that extend in the second direction, and the fourth upper package side is spaced apart from the fourth lower package side by a predetermined distance to define a second underfill region on the upper surface of the lower package. The prior art of records, individually or in combination, do not disclose nor teach “wherein the third upper package side and the third lower package side are co-planar” in combination with other limitations as recited in claim 17.
The prior art of record, Chen’364, discloses wherein the lower package comprises: a first package substrate; at least one first semiconductor chip mounted on the first package substrate; conductive connectors on the first package substrate; a first sealing member on the first package substrate and covering the at least one first semiconductor chip, wherein end portions of the conductive connectors are exposed through the first sealing member; an interposer electrically connected to the conductive connectors on the first sealing member and having upper connection pads, wherein each of the conductive connection members are on a respective one of the upper connection pads of the interposer. The prior art of records, individually or in combination, do not disclose nor teach “conductive connectors electrically connected to the at least one first semiconductor chip” in combination with other limitations as recited in claim 18.
The prior art of record, Chen’364, discloses a semiconductor package, comprising: a lower package having a first planar area and opposite first and second lower package sides that extend in a first direction; an upper package having a second planar area smaller than the first planar area, the upper package having opposite first and second upper package sides that extend in the first direction, wherein a center of the lower package is offset relative to a center of the upper package to define an underfill region on an upper surface of the lower package between the second upper package side and the second lower package side; an underfill member extending from the underfill region on the upper surface of the lower package and filling a space between the lower package and the upper package, wherein the lower package comprises: a first package substrate; at least one first semiconductor chip mounted on the first package substrate; conductive connectors on the first package substrate; a first sealing member on the first package substrate and covering the at least one first semiconductor chip, wherein end portions of the conductive connectors are exposed through the first sealing member; an interposer electrically connected to the conductive connectors on the first sealing member and having upper connection pads, wherein each of the conductive connection members is on a respective one of the upper connection pads of the interposer. The prior art of records, individually or in combination, do not disclose nor teach “conductive connectors electrically connected to the at least one first semiconductor chip, wherein the first upper package side and the first lower package side are co-planar” in combination with other limitations as recited in claim 20.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHIH TSUN A CHOU whose telephone number is (408)918-7583. The examiner can normally be reached M-F 8:00-16:00 Arizona Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571) 272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SHIH TSUN A CHOU/Primary Examiner, Art Unit 2811
Prosecution Insights