Prosecution Insights
Last updated: October 02, 2026
Application No. 18/667,899

PACKAGE COMPRISING A PASSIVE DEVICE WITH A FRONT SIDE PROTECTION LAYER

Non-Final OA §102
Filed
May 17, 2024
Examiner
SEVEN, EVREN
Art Unit
Tech Center
Assignee
Qualcomm Incorporated
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
83%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allowance Rate
559 granted / 750 resolved
+14.5% vs TC avg
Moderate +9% lift
Without
With
+8.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
32 currently pending
Career history
776
Total Applications
across all art units

Statute-Specific Performance

§101
2.7%
-37.3% vs TC avg
§103
53.7%
+13.7% vs TC avg
§102
20.8%
-19.2% vs TC avg
§112
20.8%
-19.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 750 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pat. Pub. No. 20190393153 to Wang et al. (Wang). Regarding Claims 1 and 11, Wang teaches in Figs. 1-14 at least, package 1450 comprising: a first integrated device 1413/1415; a package interposer 850 coupled to the first integrated device; and a passive device Figs. 1-6 located at least partially in the package interposer, wherein the passive device comprises: a passive device substrate 101; a plurality of trench capacitors 105-109 located at least partially in the passive device substrate; a plurality of through substrate vias 201 extending through the passive device substrate; and a protection layer 401 that is part of a first surface of the passive device, wherein the protection layer comprises an encapsulation layer or a polymer dielectric layer [0029]. Regarding Claims 2 and 12, Wang teaches the package and passive device of claims 1 and 11, wherein the passive device further comprises a dielectric layer 305 located between the protection layer and the passive device substrate. Regarding Claims 3 and 13, Wang teaches the package and passive device of claims 2 and 12, wherein the dielectric layer comprises silicon oxide and/or silicon nitride [0022,0027]. Regarding Claims 4 and 14, Wang teaches the package and passive device of claims 2 and 12, wherein the protection layer is different from the dielectric layer (organic vs. inorganic). Regarding Claims 5 and 15, Wang teaches the package and passive device of claims 1 and 11, further comprising a first plurality of post interconnects 405 coupled to the first surface of the passive device. Regarding Claims 6 and 16, Wang teaches the package and passive device of claims 5 and 15, further comprising a second plurality of post interconnects 603 coupled to a second surface of the passive device. Regarding Claims 7 and 20, Wang teaches the package and passive device of claims 1 and 11, wherein the encapsulation layer may include a mold, a resin, an epoxy and/or a filler, and wherein the polymer dielectric layer may include polyimide (PI), Polybenzoxazole (PBO) [0029], and/or Benzocyclobutene (BCB). Regarding Claim 8, Wang teaches the package of claim 1, wherein the package interposer comprises: a first metallization portion 1403; a second metallization portion 1001; and a first encapsulation layer 901 coupled to the first metallization portion and the second metallization portion, wherein the first encapsulation layer and the passive device are located between the first metallization portion and the second metallization portion (see Fig. 14). Regarding Claim 9, Wang teaches the package of claim 1, wherein the passive device includes a trench capacitor device (see Fig. 6). Regarding Claim 10, Wang teaches the package of claim 1, wherein the package is one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle ([0003], memory device which is used in any of the listed applications). Regarding Claim 17, Wang teaches the passive device of claim 11, wherein the passive device substrate comprises silicon [0014]. Regarding Claim 18, Wang teaches the passive device of claim 11, wherein the plurality of trench capacitors comprise a first electrically conductive layer 105 and a second electrically conductive layer 109. Regarding Claim 19, Wang teaches the passive device of claim 18, wherein the first electrically conductive layer comprises polysilicon [0015]. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVREN SEVEN whose telephone number is (571)270-5666. The examiner can normally be reached Mon-Fri 8:00- 5:00 Pacific. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EVREN SEVEN/ Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

May 17, 2024
Application Filed
Sep 09, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12751010
SEMICONDUCTOR DEVICE, ELECTRONIC SYSTEM INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME
3y 3m to grant Granted Sep 29, 2026
Patent 12751041
HIGH VOLTAGE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME
2y 8m to grant Granted Sep 29, 2026
Patent 12751068
SILICON CARBIDE SEMICONDUCTOR DEVICE AND POWER CONVERSION APPARATUS
2y 10m to grant Granted Sep 29, 2026
Patent 12740454
MICROELECTRONIC ASSEMBLIES WITH DIRECT BONDING USING NANOTWINNED COPPER
3y 5m to grant Granted Sep 15, 2026
Patent 12740405
BIMETALLIC FUSE ELEMENT BETWEEN METAL LEVELS
2y 8m to grant Granted Sep 15, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
83%
With Interview (+8.6%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 750 resolved cases by this examiner. Grant probability derived from career allowance rate.

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