Prosecution Insights
Last updated: October 01, 2026
Application No. 18/667,983

SEMICONDUCTOR DEVICE WITH INTERCONNECTS FORMED THROUGH ATOMIC LAYER DEPOSITION

Non-Final OA §102
Filed
May 17, 2024
Priority
Jun 08, 2023 — provisional 63/471,896
Examiner
SCHOENHOLTZ, JOSEPH
Art Unit
Tech Center
Assignee
Micron Technology Inc.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
1210 granted / 1325 resolved
+31.3% vs TC avg
Minimal -5% lift
Without
With
+-4.9%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 9m
Avg Prosecution
16 currently pending
Career history
1331
Total Applications
across all art units

Statute-Specific Performance

§101
2.7%
-37.3% vs TC avg
§103
53.1%
+13.1% vs TC avg
§102
12.4%
-27.6% vs TC avg
§112
21.5%
-18.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1325 resolved cases

Office Action

§102
DETAILED ACTION This Office Action is in response to Applicant’s application 18/667,983 filed on May 17, 2024 in which claims 1 to 20 are pending. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawings The drawings submitted on May 17, 2024 have been reviewed and accepted by the Examiner. Information Disclosure Statement The Information Disclosure Statements (IDS), filed on September 25, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein has been considered by the Examiner. Notation References to patents will be in the form of [C:L] where C is the column number and L is the line number. References to pre-grant patent publications will be to the paragraph number in the form of [xxxx]. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 3, 5, 8, 11, 13, 15-17 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. 2022/0149002 (Hou). PNG media_image1.png 696 762 media_image1.png Greyscale Regarding claim 1 and referring to annotated Figures 8 and 10A, Hou discloses method for fabricating a semiconductor device assembly, comprising: providing a first semiconductor die, 900 [0025], comprising: a first layer of dielectric material, 970 [0049]; and a first conductive pad, 988 [0049], disposed in a first opening of the first layer of dielectric material, as shown; providing a second semiconductor die, 700 [0049], comprising: a second layer of dielectric material, 770 [0049]; and a second conductive pad, 788 [0049], disposed in a second opening of the second layer of dielectric material, as shown; PNG media_image2.png 620 750 media_image2.png Greyscale disposing a spacer, 992/792 [0057], at and extending from the first layer of dielectric material, as shown; aligning the first semiconductor die and the second semiconductor die such that the first layer of dielectric material faces the second layer of dielectric material, [0049], the second layer of dielectric material contacts the spacer, as shown, and the first conductive pad corresponds to the second conductive pad, as shown; and depositing, using atomic layer deposition, [0047], a conductive material, 798/998 [0049], between the first conductive pad and the second conductive pad, as shown. Regarding claim 3 which depends upon claim 1, Hou teaches the spacer is disposed at only a portion of an exposed surface of the first layer of dielectric material, see Figure 4. Regarding claim 5 which depends upon claim 1, Hou teaches the spacer comprises a dielectric material or a polymer [0057]. Regarding claim 8 and referring to annotated Figure 8 and 10A, Hou discloses a semiconductor device assembly, comprising: a first semiconductor die, 900 [0025], comprising: a first layer of dielectric material, 970 [0049]; and a first conductive pad, 988 [0049], disposed in a first opening of the first layer of dielectric material, as shown; a second semiconductor die, 700 [0038], comprising: a second layer of dielectric material, 770 [0049], facing the first layer of dielectric material as shown; and a second conductive pad, 788 [0049], disposed in a second opening of the second layer of dielectric material, as shown, and corresponding to the first conductive pad, as shown; a spacer, 992/792 or 997 [0057], disposed at and extending from the first layer of dielectric material to the second layer of dielectric material, as shown; and a conductive material, 999 [0054-55], disposed between the first conductive pad and the second conductive pad, as shown, to implement an interconnect electrically coupling the first semiconductor die and the second semiconductor die, as shown, the conductive material at least partially extending into a gap between the first layer of dielectric material and the second layer of dielectric material, as shown. Regarding claim 11 which depends upon claim 8, Hou teaches the first conductive pad is copper [0042], and the conductive material comprise different conductive materials, e.g., noble metal [0055]. Regarding claim 13 which depends upon claim 8, at Figure 10A Hou teaches the spacer is disposed at only a portion of a surface of the first layer of dielectric material that faces the second layer of dielectric material. Regarding claim 15 which depends upon claim 8, Hou teaches the spacer comprises a polymer or a dielectric material [0057]. Regarding claim 16 which depends upon claim 8, Hou teaches the spacer has a thickness less than 0.5 microns, i.e. two monolayers of a SAM [0035, 46, 57]. Regarding claim 17 which depends upon claim 8, Hou teaches the conductive material is formed using an atomic layer deposition process [0036]. Regarding claim 19 which depends upon claim 8, Hou teaches the conductive material is a tin-free and lead-free material [0055]. Allowable Subject Matter Claims 2, 4, 6-7, 9-10, 12, 14 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 2 the prior art fails to disclose the method claim 1, further comprising depositing, using atomic layer deposition, a polymer or a dielectric material between the first layer of dielectric material, the second layer of dielectric material, the conductive material, and the spacer. Regarding claim 4 the prior art does not teach the method of claim 1, comprising forming a direct bond between the spacer and the second layer of dielectric material. Hou teaches the spacer reacts with the dielectric to form a doped dielectric at [0057]. Regarding claim 6 the prior art fails to teach the method of claim 1, wherein the first conductive pad comprises copper and the conductive material comprises cobalt. Regarding claim 7 the prior art fails to teach the method of claim 1, further comprising thinning the spacer using chemical-mechanical planarization. Regarding claim 9 the prior art does not teach the device of claim 8, wherein the first conductive pad is recessed from the first layer of dielectric material. Claim 10 depends upon claim 9 and is allowable on that basis. Regarding claim 12 the prior art fails to teach the device of claim 11, wherein the first conductive pad comprises copper and the conductive material comprises cobalt. Regarding claim 14 the prior art fails to teach the device of claim 8, further comprising a polymer or a dielectric material disposed between the first layer of dielectric material, the second layer of dielectric material, the conductive material, and the spacer. Regarding claim 18 the prior art fails to disclose the device of claim 8, wherein the interconnect is continuous between the first conductive pad and the second conductive pad and is void of metal-metal bonds. Claim 20 is allowed. The following is an examiner’s statement of reasons for allowance: Regarding claim 20 the prior art fails to disclose the method of claim 20 comprising using atomic layer deposition, a polymer or a dielectric material at least partially between the first layer of dielectric material and the second layer of dielectric material. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is listed on the notice of references cited. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joe Schoenholtz whose telephone number is (571)270-5475. The examiner can normally be reached M-Thur 7 AM to 7 PM PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ms. Yara Green can be reached at (571) 272-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /J.E. Schoenholtz/Primary Examiner, Art Unit 2893
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Prosecution Timeline

May 17, 2024
Application Filed
Sep 10, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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NITRIDE SEMICONDUCTOR DEVICE
3y 0m to grant Granted Sep 29, 2026
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SEMICONDUCTOR PACKAGE
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2y 10m to grant Granted Sep 15, 2026
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STACKED INTEGRATED CIRCUIT DEVICES WITH FACE-TO-FACE CONNECTIONS BETWEEN LOGIC AND MEMORY DIES
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
86%
With Interview (-4.9%)
1y 9m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1325 resolved cases by this examiner. Grant probability derived from career allowance rate.

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