DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species 2 and Claims 1-4 and 7-11 in the reply filed on 8/27/2026 is acknowledged.
Claims 5-6 and 12-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 8/27/2026.
Information Disclosure Statement
Acknowledgement is made of Applicant's Information Disclosure Statement (IDS) from PTO-1449. The IDS has been considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4 and 7-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites, “measuring capacitances across the one or more dielectric structures, wherein the measured capacitances represent measures corresponding to existence and/or amount of bonding voids between the carrier wafer and the semiconductor wafer and a remaining thickness of the semiconductor wafer.” It is unclear how measuring capacitances across only one dielectric structure would provide information about bonding voids or thickness of the wafer. One would either require a series of measurements across different points on the wafer, or one has to compare the measurements to a preset value (which is predetermined by measuring the capacitance across a known bonded wafer without any voids), to determine the presence of voids or a variation in thickness in the bonded structure.
Furthermore, Claim 1 recites “thickness control structures” and “dielectric structures” in lines 5 and 9 respectively. It is unclear if they represent two different elements with different physical structures or if they represent the same structure. For example, in Fig. 1, they appear to be the same. For examination purposes, they will be treated as two different elements with different physical structures, as shown in elected species 2, Fig. 4.
For the above reasons, Claim 1 is indefinite and hence rejected. Claims 2-4 and 7-11 depend from claim 1 and inherit the same indefiniteness.
Claim 8 recites the limitation wherein, “stopping thinning and disposing the semiconductor wafer where a variation of the capacitances exceeds a predetermined threshold value.” It is unclear how the threshold value is determined. The metes and bounds of the limitation is unclear. Hence, the claim is indefinite and rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 8-9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2022/0157667 A1), and further in view of Shimizu et al. (US 2015/0214123 A1).
Re Claim 1, Kim teaches a method of manufacturing a semiconductor device, the method comprising:
obtaining a carrier wafer (23, Figs. 19A-19B, para [0232]);
obtaining a semiconductor wafer (11, Figs. 19A-19B, para [0237]) to perform thinning,
wherein the semiconductor wafer (11) includes one or more thickness control structures (19, Figs. 19A-19B, para [0238]) with a targeted thickness (final thickness of wafer 11 in Fig. 19B) such that the one or more thickness control structures are exposed (11 is exposed in Fig. 19B) when the semiconductor is thinned to the targeted thickness (see Fig. 19B); and
wherein the semiconductor wafer (11) includes one or more dielectric structures (65, Figs, 19A-19B, para [0234]) with a thickness greater than or equal to the targeted thickness (see Fig. 19A);
bonding the carrier wafer (23) with an active side of the semiconductor wafer (bottom side of 11, Figs. 19A-19B);
thinning the semiconductor wafer (Fig. 19B) until the one or more dielectric structures are exposed (65 is exposed, see Fig. 19B);
Kim does not disclose the following:
measuring capacitances across the one or more dielectric structures, wherein the measured capacitances represent measures corresponding to existence and/or amount of bonding voids between the carrier wafer and the semiconductor wafer and a remaining thickness of the semiconductor wafer.
Related art Shimizu teaches a method of determining the thicknesses of wafer by measuring the capacitance across it (Fig. 1, paras [0051] – [0054]). It would have been prima facie obvious to one of ordinary skill in the art to measure the variation in thickness of the bonded wafers of Kim, using the capacitance technique provided by Shimizu. For example, one can measure the capacitance of the bonded wafers across multiple positions, including the dielectric structures of Kim, and can compare the variation in capacitance to determine voids or the remaining thickness. One can also pre-measure the capacitance across a known bonded wafer without any voids and compare the present measurements to a known predetermined value, thus estimating the final thickness of the wafer and/or the presence of any voids between the bonded wafers. The use of a known capacitance-technique for its known purpose of measuring the variation in thickness of a wafer is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Re Claim 2, Kim modified by Shimizu teaches the method of claim 1, wherein obtaining the semiconductor wafer includes:
forming one or more measurement vias on an active surface of the semiconductor wafer (opening in wafer 11 where 65 will be formed, Fig. 19A),
wherein the one or more measurement vias have a depth matching the thickness (depth of the opening where 65 will be formed, matching the thickness of 65, Fig. 19A); and
filling the one or more measurement vias with the one or more dielectric structures (opening is filled with 65, Fig. 19A).
Re Claim 3, Kim modified by Shimizu teaches the method of claim 1, wherein the targeted thickness is measured from an active surface of the semiconductor wafer toward an inactive surface thereof (see Figs. 19A-19B).
Re Claim 8, Kim modified by Shimizu teaches the method of claim 1, but does not explicitly disclose the following:
stopping thinning and disposing the semiconductor wafer where a variation of the capacitances exceeds a predetermined threshold value.
However, one of ordinary skill in the art would realize that the expected capacitance for a bonded wafer with minimal/no voids and minimum thickness variation would be known during the manufacturing process, as it is a standard industry practice for making wafers that are consistent in terms of uniformity, thickness and device performance. Any capacitive measurements that exceeds the expected value would imply a bad bonding and/or presence of voids, which would result in stopping the thinning process and discarding the bad wafer.
Re Claim 9, Kim modified by Shimizu teaches the method of claim 1, further comprising:
bonding the thinned semiconductor wafer (thinned wafer 11, Fig. 19B) to a second wafer (“2nd wafer 11” on top of “1st wafer 11”, see Fig. 20).
Re Claim 11, Kim modified by Shimizu teaches the method of claim 1, wherein:
the semiconductor wafer (11, Fig. 19B) includes scribe zones (73, Figs. 21A-21B, para [0242]) between groupings of circuits (see Figs. 21A-21B);
the dielectric structures (65, Figs, 19A-19B) are located in the scribe zones (compare Figs 19B and 21A); and further comprising:
dicing the thinned semiconductor wafer at the scribe zones (Fig. 21A, para [0249]) to singulate semiconductor dies that each have a grouping of the circuits (see Fig. 21B).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2022/0157667 A1) and Shimizu et al. (US 2015/0214123 A1), and further in view of Farnworth et al. (US 2004/0113283 A1).
Re Claim 4, Kim modified by Shimizu teaches the method of claim 1, and teaches that the thickness control structures (19, Figs. 19A-19B) are conducting vias and hence does not disclose that the one or more thickness control structures (19, Figs. 19A-19B) are dielectric so as to allow measurement of capacitance across the one or more thickness control structures.
Related art Farnworth teaches similar thickness control structures (28P, Figs.1G-1H, para [0141]) which are made of dielectric polymer and can allow capacitance measurements by the method of Kim modified by Shimizu.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the method of Kim modified by Shimizu, such that there are additional thickness control structures between the individual circuits as shown by Farnworth, as that would not only increase the accuracy of the thickness of the wafer during the thinning process but will also provide a path for singulating the individual dies (as shown in Fig. 1K, Farnworth) in a later manufacturing step.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2022/0157667 A1) and Shimizu et al. (US 2015/0214123 A1), and further in view of Sanuki et al. (US 2021/0296298 A1).
Re Claim 10, Kim modified by Shimizu teaches the method of claim 9, but does not disclose that bonding the thinned semiconductor wafer to the second wafer includes bonding memory array circuits to array control circuits, as Kim does not explicitly disclose the type of circuit elements.
Related art Sanuki teaches a similar bonded wafer (Fig. 1), where the first wafer (W1, compare Figs. 1 and 15) consists of control chips (101, Fig. 1, para [0120]) and the second wafer (W2, compare Figs. 1 and 15) consists of memory chips (102, Fig. 1, para [0120]). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the method of Kim modified by Shimizu, such that the bonded wafers include a memory chip bonded to a control chip as disclosed by Sanuki. The use of a known device architecture for bonded wafers for its known purpose to build a memory device is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Allowable Subject Matter
Claim 7 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 7 is allowable for at least the reasons of, “measuring the capacitances across the one or more dielectric structures includes: placing the bonded wafers on a bonding chuck such that the carrier wafer touches the bonding chuck; and placing probe pads on the one or more exposed dielectric structures, wherein the bonding chuck and the probe pads represent opposing conductive plates that provide the capacitances across the one or more dielectric structures.” Shimizu teaches that the probes (probes 1, Fig. 1) act as the conductive plates of the capacitor (para [0052]). However, the probes do not contact the wafer and hence does not disclose the above limitation which requires the carrier wafer touching the bonding chuck. Related art Spath (US 2015/0279748 A1) also teaches a contact-less capacitance measurement technique across a wafer (Fig. 8B, para [0067]) and thus fails to teach the above limitation. Therefore, the limitation of claim 7 as a whole is neither anticipated nor made obvious by the prior art of record in the Examiner’s opinion, when taken in context of the independent claim 1.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PINAKI DAS whose telephone number is (703)756-5641. The examiner can normally be reached M-F 8-5 EST.
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
