DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 15 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhu et al. (U.S. 2015/0041917 A1, hereinafter refer to Zhu)
Regarding Claim 15: Zhu discloses a method of forming a semiconductor device (see Zhu, Figs.3-4 and 9 as shown above and ¶ [0003]), comprising:
forming a plurality of active regions (302) in a substrate (see Zhu, Figs.3-4 as shown above);
implanting semiconductor dopant materials into each one of the plurality of active regions (302) to form a plurality of doped regions (S/D) in each one of the plurality of active regions (302) (see Zhu, Figs.3-4 as shown above);
forming, above each one of the plurality of active regions (302), one or more gate structures (304), each one of the one or more gate structures (304) being disposed between two doped regions of the plurality of doped regions (S/D) (see Zhu, Figs.3-4 as shown above);
interconnecting the one or more gate structures of the plurality of active regions with a first metal wiring layer (G) (see Zhu, Figs.3-4 as shown above); and
interconnecting a plurality of fingers of an intermediate wiring layer (IN/OUT) with the plurality of doped regions (S/D) of each one of the plurality of active regions, respectively (see Zhu, Figs.3-4 as shown above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5, 7, and 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu et al. (U.S. 2015/0041917 A1, hereinafter refer to Zhu) in view of Guo et al. (U.S. 2012/0197593 A1, hereinafter refer to Guo).
Regarding Claim 1: Zhu discloses a semiconductor device (see Zhu, Figs.3-4 and 9 as shown below and ¶ [0003]), comprising:
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a first transistor region (300a) (see Zhu, Figs.3-4 as shown above), comprising:
a first active region (302a) of the semiconductor device, the first active region (302a) including one or more first transistor source regions and one or more first transistor drain regions (see Zhu, Figs.3-4 as shown above), and
one or more first transistor gate structures (304a) disposed above the first active region (302a) (see Zhu, Figs.3-4 as shown above);
a second transistor region (300b) (see Zhu, Figs.3-4 as shown above), comprising:
a second active region (302b) disposed in the substrate and physically separated from the first active region (302a), the second active region (302b) including one or more second transistor source regions and one or more second transistor drain regions (see Zhu, Figs.3-4 as shown above), and
one or more second transistor gate structures (304b) disposed above the second active region (302b), the one or more second transistor gate structures (304b) being physically separated from the one or more first transistor gate structures (304a) (see Zhu, Figs.3-4 as shown above);
a first metal wiring layer (G) having one or more fingers that are connected to the one or more first transistor gate structures (304a) and the one or more second transistor gate structures (304b), respectively (see Zhu, Figs.3-4 as shown above);
an intermediate wiring layer (IN/OUT) having one or more first fingers (IN) and one or more second fingers (OUT), wherein the one or more first transistor source regions and the one or more second transistor source regions are connected to the one or more first fingers (IN), respectively, and the one or more first transistor drain regions and the one or more second transistor drain regions are connected to the one or more second fingers (OUT), respectively (see Zhu, Figs.3-4 as shown above).
Zhu is silent upon explicitly disclosing wherein a second metal wiring layer having a source finger, a drain finger, and a gate finger, wherein the source finger is connected to the one or more first fingers of the intermediate wiring layer, the drain finger is connected to the one or more second fingers of the intermediate wiring layer, and the gate finger is connected to the one or more fingers of the first metal wiring layer.
For support see Guo, which teaches wherein a second metal wiring layer (M3/VIA-2) having a source finger (M3/VIA-2), a drain finger (M3/VIA-2), and a gate finger (M3/VIA-2), wherein the source finger (M3/VIA-2) is connected to the one or more first fingers of the intermediate wiring layer (M2/VIA-1), the drain finger (M3/VIA-2) is connected to the one or more second fingers of the intermediate wiring layer (M2/VIA-1), and the gate finger (M3/VIA-2) is connected to the one or more fingers of the first metal wiring layer (M2/VIA-1) (see Guo, Figs.4-5 as shown below, ¶ [0008], ¶ [0038]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Zhu and Guo to enable a second metal wiring layer having a source finger, a drain finger, and a gate finger, wherein the source finger connected to the one or more first fingers of the intermediate wiring layer, the drain finger connected to the one or more second fingers of the intermediate wiring layer, and the gate finger connected to the one or more fingers of the first metal wiring layer as taught by Guo in order to get the delta channel width of the nano-scale metal-oxide-semiconductor field-effect transistor (MOSFET), and further to determine the effective channel width.
Regarding Claim 2: Zhu as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Zhu and Guo further teaches wherein the first active region (300a) and the second active region (300b) are aligned along a first direction, the one or more first transistor source regions are respectively aligned with the one or more second transistor source regions along the first direction, the one or more first transistor drain regions are respectively aligned with the one or more second transistor drain regions along the first direction, and the one or more first transistor gate structures (304a) are respectively aligned with the one or more second transistor gate structures (304b) along the first direction (see Zhu, Figs.3-4 as shown above).
Regarding Claim 3: Zhu as modified teaches a semiconductor device as set forth in claim 2 as above. The combination of Zhu and Guo further teaches wherein the one or more first transistor source regions and the one or more second transistor source regions share, through the one or more first fingers of the intermediate wiring layer (IN/OUT) and the source finger of the second metal wiring layer (M3/VIA-2), a same source operating voltage (see Zhu, Figs.3-4 as shown above and see Guo, Figs.4-5 as shown above),
wherein the one or more first transistor drain regions and the one or more second transistor drain regions share, through the one or more second fingers (OUT) of the intermediate wiring layer (IN/OUT) and the drain finger of the second metal wiring layer (M3/VIA-2), a same drain operating voltage (see Zhu, Figs.3-4 as shown above and see Guo, Figs.4-5 as shown above), and
wherein the one or more first transistor gate structures and the one or more second transistor gate structures share, through the one or more fingers of the first metal wiring layer (G) and the gate finger of the second metal wiring layer (M3/VIA-2), a same gate operating voltage (see Zhu, Figs.3-4 as shown above and see Guo, Figs.4-5 as shown above).
Regarding Claim 4: Zhu as modified teaches a semiconductor device as set forth in claim 2 as above. The combination of Zhu and Guo further teaches wherein the one or more first transistor source regions, the one or more first transistor drain regions, and the one or more first transistor gate structures are aligned along a second direction orthogonal to the first direction, and wherein the one or more second transistor source regions, the one or more second transistor drain regions, and the one or more second transistor gate structures are aligned along the second direction (see Zhu, Figs.3-4 as shown above).
Regarding Claim 5: Zhu as modified teaches a semiconductor device as set forth in claim 3 as above. The combination of Zhu and Guo further teaches wherein one of the one or more first transistor drain regions is disposed between adjacent two first transistor source regions of the one or more first transistor source regions along the second direction, and wherein one of the one or more second transistor drain regions is disposed between adjacent two second transistor source regions of the one or more second transistor source regions along the second direction (see Zhu, Figs.3-4 as shown above).
Regarding Claim 7: Zhu as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Zhu and Guo further teaches wherein the one or more first transistor gate structures and the one or more second transistor gate structures have a same gate width and a same gate length (see Zhu, Figs.3-4 as shown above).
Regarding Claim 10: Zhu as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Zhu and Guo further teaches a third transistor region (300c) (see Zhu, Figs.3-4 and 9 as shown above), comprising:
a third active region (302c) disposed in the substrate and physically separated from the first and the second active regions (302a/302b), the third active region including one or more third transistor source regions and one or more third transistor drain regions (see Zhu, Figs.3-4 and 9 as shown above), and
one or more third transistor gate structures disposed above the third active region, the one or more third transistor gate structures being physically separated from the one or more first transistor gate structures and the one or more second transistor gate structures (see Zhu, Figs.3-4 and 9 as shown above),
wherein the one or more fingers of the first metal wiring layer (G) are connected to the one or more first transistor gate structures, the one or more second transistor gate structures, and the one or more third transistor gate structures, respectively (see Zhu, Figs.3-4 and 9 as shown above), and
wherein the one or more third transistor source regions are respectively connected to the one or more first fingers (IN), and the one or more third transistor drain regions are respectively connected to the one or more second fingers (OUT) (see Zhu, Figs.3-4 and 9 as shown above).
Regarding Claim 11: Zhu as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Zhu and Guo further teaches wherein the first active region (302a) includes two first transistor source regions, one first transistor drain region, and two first transistor gate structures, the one first transistor drain region being disposed between the two first transistor source regions and each of the two first transistor gate structures being disposed between the one first transistor drain region and corresponding one of the two first transistor source regions (see Zhu, Figs.3-4 and 9 as shown above).
Regarding Claim 12: Zhu as modified teaches a semiconductor device as set forth in claim 11 as above. The combination of Zhu and Guo further teaches wherein the second active region (302b) includes two second transistor source regions, one second transistor drain region, and two second transistor gate structures, the one second transistor drain region being disposed between the two second transistor source regions and each of the two second transistor gate structures being disposed between the one second transistor drain region and corresponding one of the two second transistor source regions (see Zhu, Figs.3-4 and 9 as shown above).
Regarding Claim 13: Zhu as modified teaches a semiconductor device as set forth in claim 11 as above. The combination of Zhu and Guo further teaches wherein both two first transistor source regions are connected, respectively through two fingers of the one or more first fingers of the intermediate wiring layer (IN), to the source finger of the second metal wiring layer (M3/VIA-2) (see Zhu, Figs.3-4 and 9 as shown above and see Guo, Figs.4-5 as shown above), and
wherein both two first transistor gate structures are connected to a first gate finger of the first metal wiring layer (G) (see Zhu, Figs.3-4 and 9 as shown above).
Regarding Claim 14: Zhu as modified teaches a semiconductor device as set forth in claim 13 as above. The combination of Zhu and Guo further teaches wherein both two second transistor source regions are connected, respectively through the two fingers of the one or more first fingers of the intermediate wiring layer (IN), to the source finger of the second metal wiring layer (M3/VIA-2) (see Zhu, Figs.3-4 and 9 as shown above and see Guo, Figs.4-5 as shown above), and
wherein both two second transistor gate structures are connected to a second gate finger of the first metal wiring layer (G) (see Zhu, Figs.3-4 and 9 as shown above).
Claim(s) 16 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu et al. (U.S. 2015/0041917 A1, hereinafter refer to Zhu) as applied to claim 15 above, and further in view of Guo et al. (U.S. 2012/0197593 A1, hereinafter refer to Guo).
Regarding Claim 16: Zhu discloses a method of forming a semiconductor device as applied to claim 15 above. Zhu further teaches wherein interconnecting the first metal wiring layer (G) with another plurality of fingers of the intermediate wiring layer (IN/OUT) (see Zhu, Figs.3-4 as shown above).
Zhu is silent upon explicitly disclosing wherein interconnecting a first group of the plurality of fingers of the intermediate wiring layer with a source finger of a second metal wiring layer;
interconnecting a second group of the plurality of fingers of the intermediate wiring layer with a drain finger of the second metal wiring layer; and
interconnecting the intermediate wiring layer with a gate finger of the second metal wiring layer.
For support see Guo, which teaches wherein interconnecting a first group of the plurality of fingers of the intermediate wiring layer (M2/VIA-1) with a source finger of a second metal wiring layer (M3/VIA-2) (see Guo, Figs.4-5 as shown above, ¶ [0008], ¶ [0038]);
interconnecting a second group of the plurality of fingers of the intermediate wiring layer (M2/VIA-1) with a drain finger of the second metal wiring layer (M3/VIA-2) (see Guo, Figs.4-5 as shown above, ¶ [0008], ¶ [0038]); and
interconnecting the intermediate wiring layer (M2/VIA-1) with a gate finger of the second metal wiring layer (M3/VIA-2) (see Guo, Figs.4-5 as shown above, ¶ [0008], ¶ [0038]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Zhu and Guo to enable interconnecting a first group of the plurality of fingers of the intermediate wiring layer with a source finger of a second metal wiring layer, interconnecting a second group of the plurality of fingers of the intermediate wiring layer with a drain finger of the second metal wiring layer, and interconnecting the intermediate wiring layer with a gate finger of the second metal wiring layer as taught by Guo in order to get the delta channel width of the nano-scale metal-oxide-semiconductor field-effect transistor (MOSFET), and further to determine the effective channel width.
Regarding Claim 19: Zhu as modified teaches a method of forming a semiconductor device as set forth in claim 16 as above. The combination of Zhu and Guo further teaches wherein the plurality of active regions (302) are fabricated to be aligned along a first direction, the plurality of doped regions (S/D) in each one of the plurality of active regions are aligned along a second direction orthogonal to the first direction, and the one or more gate structures (304) are aligned along the first direction in each one of the plurality of active regions (see Zhu, Figs.3-4 as shown above).
Regarding Claim 20: Zhu as modified teaches a method of forming a semiconductor device as set forth in claim 16 as above. The combination of Zhu and Guo further teaches wherein forming a first plurality of via connections above the first metal wiring layers, wherein the intermediate wiring layer is connected to the first metal wiring layers through the first plurality of via connections (see Guo, Figs.4-5 as shown above); and
forming a second plurality of via connections above the intermediate wiring layer, wherein the second metal wiring layer is connected to the intermediate wiring layer through the second plurality of via connections (see Guo, Figs.4-5 as shown above).
Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Zhu et al. (U.S. 2015/0041917 A1, hereinafter refer to Zhu) and Guo et al. (U.S. 2012/0197593 A1, hereinafter refer to Guo) as applied to claim 1 above, and further in view of Peng et al. (U.S. 2017/0110405 A1, hereinafter refer to Peng).
Regarding Claim 6: Zhu as modified teaches a semiconductor device as applied to claim 1 above. The combination of Zhu and Guo is silent upon explicitly disclosing wherein each of the first metal wiring layer, the intermediate wiring layer, and the second metal wiring layer is made of conductive materials including copper, tungsten, molybdenum, nickel, titanium, tantalum, platinum, silver, gold, ruthenium, iridium, rhenium, rhodium, or alloys thereof.
For support see Peng, which teaches wherein each of the first metal wiring layer, the intermediate wiring layer, and the second metal wiring layer is made of conductive materials including copper, tungsten, molybdenum, nickel, titanium, tantalum, platinum, silver, gold, ruthenium, iridium, rhenium, rhodium, or alloys thereof (see Peng, ¶ [0032], ¶ [0065], ¶ [0066], and ¶ [0072]).
The combination of Zhu and Guo teaches the claimed invention except for the materials of first metal wiring layer, the intermediate wiring layer, and the second metal wiring layer. Thus, it would have been obvious to one having ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Zhu, Guo, and Peng to enable the known materials as taught by Peng in order to form the first metal wiring layer, the intermediate wiring layer, and the second metal wiring layer, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
Claim(s) 8 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu et al. (U.S. 2015/0041917 A1, hereinafter refer to Zhu) and Guo et al. (U.S. 2012/0197593 A1, hereinafter refer to Guo) as applied to claims 1 and 16 above, and further in view of Kawa et al. (U.S. 2013/0026571 A1, hereinafter refer to Kawa).
Regarding Claim 8: Zhu as modified teaches a semiconductor device as applied to claim 1 above. The combination of Zhu and Guo is silent upon explicitly disclosing wherein the first active region and the second active region are isolated by a shallow trench isolation (STI) region disposed in the substrate.
For support see Kawa, which teaches wherein the first active region and the second active region are isolated by a shallow trench isolation (STI) region disposed in the substrate (see Kawa, Fig.4 and ¶ [0053]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Zhu, Guo, and Kawa to enable the combination of Zhu’s and Guo’s first active region and second active region to be isolated by a shallow trench isolation (STI) region disposed in the substrate as taught by Kawa in order to prevent current leakage as a result of parasitic transistors.
Regarding Claim 17: Zhu as modified teaches a method of forming a semiconductor device as applied to claim 16 above. The combination of Zhu and Guo further teaches wherein forming the plurality of doped regions (S/D) including forming a plurality of source regions and a plurality of drain regions in each one of the plurality of active regions, wherein the plurality of source regions and the plurality of drain regions are alternatively aligned in series in the substrate, wherein each one of the one or more gate structures (304) is disposed between a corresponding source region and a corresponding drain region, and wherein forming the plurality of active regions (302) includes implanting dopant materials into each one of the plurality of active regions (302) in the substrate (see Zhu, Figs.3-4 as shown above).
The combination of Zhu and Guo is silent upon explicitly disclosing wherein the plurality of active regions being physically separated by corresponding STI regions disposed in the substrate.
For support see Kawa, which teaches wherein the plurality of active regions being physically separated by corresponding STI regions disposed in the substrate (see Kawa, Fig.4 and ¶ [0053]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Zhu, Guo, and Kawa to enable the combination of Zhu’s and Guo’s the plurality of active regions to be physically separated by corresponding STI regions disposed in the substrate as taught by Kawa in order to prevent current leakage as a result of parasitic transistors.
Regarding Claim 18: Zhu as modified teaches a method of forming a semiconductor device as applied to claim 17 as above. The combination of Zhu, Guo, and Kawa further teaches wherein the plurality of source regions disposed in each one of the plurality of active regions are connected to the first group of the plurality of fingers of the intermediate wiring layer, respectively, and wherein the plurality of drain regions disposed in each one of the plurality of active regions are connected to the second group of the plurality of fingers of the intermediate wiring layer, respectively (see Zhu, Figs.3-4 as shown above).
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Zhu et al. (U.S. 2015/0041917 A1, hereinafter refer to Zhu) and Guo et al. (U.S. 2012/0197593 A1, hereinafter refer to Guo) as applied to claim 1 above, and further in view of Onda (U.S. 2007/0241810 A1, hereinafter refer to Onda).
Regarding Claim 8: Zhu as modified teaches a semiconductor device as applied to claim 1 above. The combination of Zhu and Guo is silent upon explicitly disclosing wherein the semiconductor device is a volatile memory device including a dynamic random access memory (DRAM) and/or a static random access memory (SRAM).
For support see Onda, which teaches wherein the semiconductor device is a volatile memory device including a dynamic random access memory (DRAM) and/or a static random access memory (SRAM) (see Onda, Fig.3 and ¶ [0002]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Zhu, Guo, and Onda to enable the combination of Zhu’s and Guo’s semiconductor device for forming a volatile memory device including a dynamic random access memory (DRAM) and/or a static random access memory (SRAM) as taught by Onda in order to obtain memory device such as a DRAM (Dynamic Random Access Memory).
Conclusion
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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