DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/30/3036 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable Dono et al. (US 2021/0104293 A1) in view of Yoon et al. (US 2014/0126301 A1) and further in view of Busi et al. (US 2017/0110205 A1).
Claim 17: Dono teaches a memory device comprising:
a base die (e.g., interface/logic die 104, Fig. 1);
and a plurality of core dies (e.g., item 106) stacked on the base die and connected to the base die through a plurality of through-silicon vias (TSV) (e.g., [0017], [0021], wherein each of the plurality of core dies comprises:
a plurality of memory banks (e.g., [0027]-[0028]) each having a plurality of rows corresponding to a plurality of row addresses, wherein the base die comprises: a built-in self-test (BIST) circuit (e.g., [0024], [0031]-[0033]). Dono further teaches performing tests on the core dies using circuitry on the interface die, including a BIST sequencer that generates test sequences and memory addresses, writes test data to the core-die memory, subsequently reads the data, and uses an error-catch circuit to compare the read data and generate result information. See ¶¶[0019], [0024], [0031]-[0036].
Not explicitly taught by Dono is selecting a first and second bank from the plurality for same-row parallel testing, comparing the outputs of those two selected banks against each other, selecting fewer target banks than the total number of banks, and storing the first/second bank selections in the claimed target-bank table.
However, Yoon teaches a four-bank memory in which two banks are selected at a time during test mode, those two banks operate simultaneously at the same row address, identical data are written/read, and the two bank outputs are compared to generate a fail signal. See ¶¶[0030], [0038]-[0043]. Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to modify Dono’s HBM BIST arrangement to employ Yoon’s paired-bank comparative test because both references concern built-in/on-device testing of memory, and Yoon expressly identifies its paired-bank procedure as a technique for quickly detecting failed rows and reducing repair test time. See Yoon ¶¶[0019]-[0020]. The modification merely uses Yoon’s known memory-test procedure in Dono’s known HBM BIST architecture and yields the predictable result of detecting faults by comparison of corresponding outputs of simultaneously tested banks. Busi further teaches using stored bank-related tables in a BIST address generator and using those tables to dynamically determine bank/word-line test addresses. See ¶¶[0037]-[0038]. It would have been obvious to use Busi’s table-driven address-generation technique to organize the selected-bank/row combinations in the modified Dono/Yoon system for systematic address coverage and reduced test time.
Regarding claim 19, Dono further teaches that the memory device may include a plurality of core dies coupled to the interface die and that test operations may be performed on memory cells of one or more of the core dies. See Dono ¶¶[0021], [0045]. Dono further teaches that the BIST sequencer performs testing sequentially by testing a particular address, incrementing the address, and thereafter performing another test. See Dono ¶[0032]. Yoon teaches performing parallel tests on selected memory banks with respect to a common row address and repeating such testing while changing the row address and/or bank address. See Yoon ¶¶[0038]-[0045].
It would have been obvious to one of ordinary skill in the art to apply Yoon’s parallel-bank test procedure to the plurality of core dies of Dono and to sequentially perform such parallel testing for successive row addresses with respect to the respective core dies, because Dono expressly teaches sequential address-based BIST operations across memory cells of one or more core dies. Such an arrangement would have predictably provided systematic test coverage of the memory banks in each stacked core die using the existing BIST circuitry.
Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yoon and further in view of Busi et al.
Claim 20: Yoon teaches a memory device comprising:
a plurality of memory banks each having a plurality of rows corresponding to a plurality of row addresses (e.g., see BK0-BK3, Fig. 3 - ¶¶[0028]-[0029]); and a test circuit configured to: selectively activating two banks from the four available banks during test mode (¶[0030]); repeatedly performing a test in which the same data are written to the selected banks, read from those banks, and compared to generate a fail signal (¶¶[0041]-[0045]); storing the associated bank and row information responsive to a detected failure (¶¶[0036], [0044]); and using the stored failure information to identify failed memory regions for repair (¶¶[0046], [0048]-[0049]). Yoon further teaches that the selected banks constitute two banks from four available memory banks, thereby teaching a number of selected target banks that is less than the number of memory banks. ¶[0030], Table 1.
Not explicitly taught by Yoon is determining and storing the selected-bank/row relationships in a target bank table. However, Busi teaches a BIST address generator that generates bank-related tables before testing and uses a selected table to dynamically determine the bank/word-line test addresses during testing. ¶¶[0037]-[0038]. Therefore, it would have been obvious, to a POSITA, before the effective filing date of the claimed invention, to implement Yoon’s known bank-selection relationship using Busi’s table-driven test-address arrangement in order to organize the bank/row test sequence and reduce unnecessary test addresses and test time, as expressly taught by Busi. The resulting system would predictably maintain information identifying the selected banks for respective row addresses and use that information in conducting the repeated tests.
Allowable Subject Matter
Claims 1-16 are allowed.
The following is an examiner’s statement of reasons for allowance: The prior arts of record fail to teach or suggest, alone or in combination, a memory device including a built-in self-test (BIST) circuit configured to select a first target bank and a second target bank for each of a plurality of row addresses such that each of the plurality of memory banks is selected as both the first target bank and the second target bank at least once, wherein the first target bank and the second target bank are selected based on a target bank table configured to store information on a mapping of the first and second target banks and each of the plurality of row addresses. The prior arts further fail to teach or suggest the above limitations in combination with a fail bank table configured to store information indicating whether or not a fail occurs for each of a plurality of bank addresses corresponding respectively to the plurality of memory banks.
Accordingly, the prior arts of record do not teach or render obvious the claimed combination of limitations.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim 18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 8/31/2026
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