DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot in view of the new ground of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over DE10110272 (hereinafter Hartner) and further in view of US7178072 B2 ("Mullins").
Claim 1: Hartner teaches a memory device comprising:
a plurality of memory banks (e.g. items 11, 12, 13, 14, fig. 1) each having a plurality of rows corresponding to a plurality of row addresses (see abstract, description pages 5-6);
a built-in self-test (BIST) circuit comprising a random generator (20), address generator (40), and control device (41) that performs parallel tests on the memory banks by writing the same random data to the same row address in multiple banks and then reading it out (e.g. [0015] & [0019]);
a comparison device (30) that compares data read from different memory banks and generates an error signal (F, F') based on the result (e.g. [0017]).
Hartner fails to teach:
selecting a first and second target bank for each row address for comparison;
a built-in analysis circuit configured to update a fail bank table that records fail information for each memory bank and identifies defective banks by referring to such a table;
wherein the first target bank and the second target bank for each of the plurality of row addresses are selected based on a target table configured to store information on a mapping of the first and second target banks and each of the plurality of row addresses.
As per item (i), Hartner teaches applying the same address to all banks in parallel (description pp. 8-9), and as per item (ii), Hartner teaches a memory element (50) (e.g. fail bank table) that stores a failing address (FADR) when the error signal indicates a failure (e.g.[0017]).
However, Mullins teaches that information is stored in a "table having row and column portions, each row and column portion of the table including at least one address/error-count entry pair" for storing addresses of failed memory locations and the number of failures detected (e.g., Abstract and column 4, lines 15-25); wherein the stored information is updated to indicate whether a row spare or column spare should be assigned, or if the memory is not repairable (e.g., Column 4, lines 30-35) and the repair analysis algorithm interprets the table to determine which rows/columns are defective and need repair (e.g., Column 9, lines 45-55). Furthermore, Mullins teaches that the table includes "linking information that links an address in one table to an address in the other table." (e.g., Column 5, lines 10-20 ); wherein the table entries link row addresses to corresponding column addresses via ID fields, effectively mapping failure addresses to repair resources (e.g., Column 8, lines 40-50). Also, Mullins teach that the table represents "a portion of memory where at least one of the first type of memory spare intersects at least one of the second complementary type of memory spare." (e.g., Column 7, lines 15-25); wherein the table is sized based on the number of spare rows and columns in the memory sub-block (e.g., Column 10, lines 5-15). Finally, Mullins teach that as errors are detected, the table is updated, error counts are incremented, new entries are added, and repair decisions are made based on whether error counts exceed available spare resources (e.g., FIG. 5A-5D and column 8, lines 10-30) and the method detects "certain un-repairable memory failure conditions before initiating a repair algorithm." Column 9, lines 30-40: When the table is full and a new error does not match existing entries, the memory is tagged as unrepairable (e.g., Column 4, lines 40-50).
Therefore, POSITA, before the effective filing date of the claimed invention, to combine the teachings of Hartner and Mullins for the following reasons:
Hartner stores a failing address (FADR) in storage element (50) but does not organize this information for comprehensive repair analysis. Mullins explicitly addresses the problem of "storing only that failed memory information that is necessary to completely analyze and generate the repair information" (column 2, lines 45-50). A skilled artisan would recognize that the single-address storage of Hartner is insufficient for multi-bank repair analysis and would look to Mullins' table structure to solve this deficiency.
Hartner discloses BIST with parallel bank testing. Mullins discloses techniques for "at-speed storage of all failed memory information" and "detecting certain un-repairable memory failure conditions before initiating a repair algorithm" (column 2, lines 55-60). Combining the parallel test capability of Hartner with the efficient failure storage and analysis of Mullins would yield a more robust and efficient BIST/BISR system.
Claim 2: Hartner and Mullins teach the memory device of claim 1, but fail to teach that in the target bank table and in any previous row address and subsequent row address of any consecutive row addresses among the plurality of row addresses, the first target bank of the subsequent row address is identical to the second target bank of the previous row address, and a second target bank of the subsequent row address is different from the first target bank of the previous row address. However, these patterns are simple, logical, and well-known test sequencing strategies (e.g., round-robin, pairwise testing) used to ensure comprehensive coverage. It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to apply these standard and obvious test patterns to the framework of Hartner and Mullins once they were motivated to test banks in pairs for fault isolation. Designing a test sequence to ensure every bank is tested in both the first and second target role, and that all bank pairs are tested, requires only routine experimentation.
Claim 3: Hartner and Mullins teach the memory device of claim 1, but fail to teach that the BIST circuit is configured to select the first target bank and the second target bank such that all combinations of the first target bank and the second target bank are selected from the plurality of row addresses. However, these patterns are simple, logical, and well-known test sequencing strategies (e.g., round-robin, pairwise testing) used to ensure comprehensive coverage. It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to apply these standard and obvious test patterns to the framework of Hartner and Mullins once they were motivated to test banks in pairs for fault isolation. Designing a test sequence to ensure every bank is tested in both the first and second target role, and that all bank pairs are tested, requires only routine experimentation.
Claim 4: Hartner and Mullins teach the memory device of claim 1, but fail to teach that the comparator is configured to: initialize the fail signal, and toggle the fail signal when different bits are detected in the first data and the second data. However, Hartner teaches a comparator (30) that outputs a fail signal (F, F') based on the comparison result (abstract, description p. 10). The specific implementation detail of "initializing" and "toggling" the fail signal is a conventional and obvious design choice for a digital logic circuit generating a flag signal. Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to implement the comparator's output in this well-known manner.
As per claims 5,6, 9, 10 and 13, Hartner teaches obtaining a target row address (via address generator 40) corresponding to a fail and storing it in a memory element (50) (claim 4, description p. 10). However, Hartner fails to teach updating a fail bank table and referring to a target bank table that maps banks to row addresses. However, Mullins is directed to "methods and apparatus for storing memory test information". It explicitly teaches storing information related to failed memory cells in a "table having row and column portions, each row and column portion of the table including at least one address/error-count entry pair". This table structure is the equivalent of the claimed "fail bank table," as it stores fail information (addresses and error counts) for different portions of the memory. Mullins further teaches that this table includes "linking information that links an address in one table to an address in the other table". This linking information, which maps a failing row address to a corresponding column address for repair analysis, is the equivalent of the claimed "target bank table including information on the mapping of the first and second target banks selected for each of the plurality of row addresses" . The mapping is inherent to the table's structure and is used to determine how to allocate spare resources and the process of updating the table upon detecting a failure is central to Mullins. Figures 5A-5D and the accompanying text describe how, as errors are detected, the table is dynamically updated, error counts are incremented, new address/error-count pairs are added, and the linking information is managed.
Therefore, Hartner provides a basic BIST system that can detect failures and store a single failing address in an element (50) and a POSITA, seeking to improve this system's diagnostic and repair capabilities, would look to known solutions for managing failure information. Mullins represents such a known solution, offering a structured and efficient method for logging multiple failures and organizing them for repair analysis . It would have been an obvious design choice, to a POSITA before the effective filing date of the claimed invention, to replace Hartner's simple address storage element with the more robust table structure taught by Mullins.
As per claims 7, 8, 11 and 12, Hartner and Mullins provide the system for parallel testing and comparing data from specific bank pairs. However, Hartner fails to teach the specific logical rules for determining a "defective bank" (e.g., a bank that fails in both roles, claim 7) or a "noise bank" (e.g., a bank that fails in only one role, claim 8) based on the accumulated fail information.These decision rules are straightforward and obvious data analysis techniques. Once a person of ordinary skill in the art is tracking fail information per bank per role (as established above), applying these simple, logical rules to distinguish between a consistently failing bank and an intermittently failing one is an obvious next step. Similarly, the use of a threshold on a fail count (claims 11-12) to distinguish between permanent and intermittent defects is a well-known and obvious heuristic in the field of memory testing and failure analysis.
Claim 14: Hartner and Mullins teach the memory device of claim 1, wherein the BIST circuit is configured to perform the parallel tests by: writing the same data to the first target bank and the second target bank, and reading data stored in the first target bank and the second target bank. For instance, Hartner explicitly teaches performing parallel tests by writing the same data (from random generator 20) to the memory banks and then reading the stored data out for comparison (abstract, description pp. 8-10).
Claim 15: Hartner and Mullins teach the memory device of claim 1, but fail to teach that the comparator includes a plurality of XOR circuits, wherein the plurality of XOR circuits are disposed at a first distance from a data path of the plurality of memory banks, and wherein the built-in analysis circuit is disposed at a second distance from the data path of the plurality of memory banks, the second distance being greater than the first distance. However, Hartner teaches a comparator (30) for comparing data. The use of XOR circuits to perform a bitwise comparison is a fundamental and well-known digital design technique. The specific placement of these circuits closer to the data path than the analysis circuit is an obvious design choice made to minimize signal propagation delay, reduce routing complexity, and improve performance, which are constant objectives in circuit layout.
Claim 16: Hartner and Mullins teach the memory device of claim 1, but fail to teach that the information of the target bank table is stored at a time of manufacturing the memory device or is received from outside the memory device. However, Hartner teaches an address generator (40) that provides addresses for the test. Whether the information for the "target bank table" (i.e., the test sequence defining bank pairs) is hardcoded at manufacture or received from an external source is a non-inventive design choice based on system requirements for flexibility vs. simplicity. Both approaches were well-known in the art at the time of the invention.
As per claims 17-19, Hartner and Mullins provide the teaching of the BIST circuit, comparator, and analysis circuit (see the rejection of claim 1 above). However, Hartner fails to teach a 3D-stacked memory device with a base die and core dies connected by TSVs. However, the application of these known testing structures to a 3D-stacked memory device comprising a base die and core dies connected by TSVs would have been obvious. 3D-stacked memories were a known architecture, and it is a predictable and obvious requirement to test the memory banks within them. Integrating a BIST circuit into the base die to test core dies is a logical and obvious partitioning of function. The placement of comparator circuits (e.g., XOR trees) near the TSV data lines (claim 18) is an obvious layout optimization for the reasons stated for claim 15. Sequentially testing the plurality of core dies (claim 19) is an obvious method for managing test complexity and power consumption in a multi-die stack.
As per claim 20, this claim is a method claim that recites the same functionality as the apparatus claims. For the same reasons detailed in the rejection of claim 1 and its dependent claims, the steps of claim 20 are taught by the combination of Hartner and Mullins. Hartner performs the steps of writing the same data, reading it out, and outputting a fail signal (see the rejection of claim 1 above). However, Hartner fails to teach determining a target bank table indicating selected target banks for each row address, and updating fail information for each memory bank by referring to this table. However, Mullins teaches comparing data from specific blocks, which implies the selection of target banks. Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to manage the test using a "target bank table" and "fail information," as these are conventional data structures for test systems designed to isolate faults through comparative analysis.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 3/13/2026