DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application TW 113104893 filed in Taiwan Intellectual Property Office (TIPO) on February 7, 2024 and receipt of a certified copy thereof.
Information Disclosure Statement
The information disclosure statement (IDS) filed on May 20, 2024 and IDS filed on May 21, 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDSs are considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 8 and 9 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Li et al. US 2020/0098867.
Regarding claim 1, Li teaches a semiconductor device (e.g., 100, Fig. 1B; [28]-[36]), comprising:
a semiconductor layer (e.g., semiconductor layer including 130 and/or 140, Fig. 1B), having a channel region (e.g., 130 and/or 140, Fig. 1B, [32]);
a gate structure (e.g., 160, Fig. 1B), having a surface (e.g., surface of 160 adjacent to an upper surface of 150, Fig. 1B) to contact the semiconductor layer, wherein the gate structure overlaps the channel region of the semiconductor layer along a direction perpendicular to the surface of the gate structure (e.g., Fig. 1B);
a control-source electrode plate (e.g., 120, Fig. 1B) in contact with the semiconductor layer, wherein the control-source electrode plate (e.g., 120, Fig. 1B) covers the gate structure (e.g., 160, Fig. 1B) and the channel region (e.g., 130 and/or 140, Fig. 1B) of the semiconductor layer along the direction perpendicular to the surface of the gate structure (e.g., Fig. 1B); and
a drain electrode (e.g., 150, Fig. 1B) in contact with the semiconductor layer.
Regarding claim 4, Li teaches the semiconductor device of claim 1, wherein the semiconductor layer comprises: a first semiconductor region (e.g., 130, Fig. 1B) adjacent to the control-source electrode plate; and a second semiconductor region (e.g., 140, Fig. 1B) adjacent to the drain electrode, wherein the first semiconductor region and the second semiconductor region are of a same conductivity type (e.g., n-type, Fig. 1B).
Regarding claim 8, Li teaches the semiconductor device of claim 1, wherein the control-source electrode plate entirely overlaps the gate structure along the direction (e.g., Fig. 1B).
Regarding claim 9, Li teaches the semiconductor device of claim 1, wherein the control-source electrode plate further extends beyond a sidewall of the gate structure (e.g., Li, Fig. 1B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 8 and 9 are rejected are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. TW M598528 (the original document and a machine-generated English translation thereof are used in rejection) in view of Li et al. US 2020/0098867.
Regarding claim 1, Chen teaches a semiconductor device (e.g., 100, Fig. 1; translation pp. 2-5), comprising:
a semiconductor layer (e.g., 1, Fig. 1), having a channel region (e.g., area of 1 under the gate 5, Fig. 1; translation p. 3);
a gate structure (e.g., 5, Fig. 1), having a surface (e.g., surface of 5 contacting 1, Fig. 1) to contact the semiconductor layer, wherein the gate structure overlaps the channel region of the semiconductor layer along a direction perpendicular to the surface of the gate structure (e.g., Fig. 1);
a control-source electrode plate (e.g., 2, Fig. 1) in contact with the semiconductor layer; and
a drain electrode (e.g., 3, Fig. 1) in contact with the semiconductor layer.
Chen does not explicitly teach wherein the control-source electrode plate covers the gate structure and the channel region of the semiconductor layer along the direction perpendicular to the surface of the gate structure.
Chen, however, recognizes that the semiconductor device 100 includes a tunnel field-effect transistor and other modifications (including configurations/arrangements of components of the tunnel field-effect transistor) based on the scope of the disclosure of Chen may still be made (e.g., translation p. 6).
Li teaches a tunnel field-effect transistor (e.g., [28]-[36]), wherein the control-source electrode plate (e.g., 120, Fig. 1B) covers the gate structure (e.g., 160, Fig. 1B) and the channel region (e.g., 130 and/or 140, Fig. 1B) of the semiconductor layer along the direction perpendicular to the surface of the gate structure (e.g., Fig. 1B).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chen to include wherein the control-source electrode plate covers the gate structure and the channel region of the semiconductor layer along the direction perpendicular to the surface of the gate structure as suggested by Li because a configuration/arrangement of components of a tunnel field-effect transistor is a matter of obvious design choice, and thus, the modification can be achieved by the general skill of a worker in the art through ordinary means of routine work, for example.
Regarding claim 2, Chen in view of Li teaches the semiconductor device of claim 1, wherein the drain electrode does not overlap the gate structure along the direction (e.g., Chen, Fig. 1).
Regarding claim 3, Chen in view of Li teaches the semiconductor device of claim 1, wherein one of the control-source electrode plate (e.g., Chen, 2, Fig. 1) and the drain electrode forms a Schottky contact with the semiconductor layer (e.g., Chen, 1, Fig. 1; translation, p. 3), and the other of the control-source electrode plate and the drain electrode (e.g., Chen, 3, Fig. 1) forms an Ohmic contact with the semiconductor layer (e.g., Chen, 1, Fig. 1; translation, p. 3).
Regarding claim 4, Chen in view of Li teaches the semiconductor device of claim 1, wherein the semiconductor layer comprises: a first semiconductor region (e.g., Chen, first semiconductor region of 1 adjacent to 2, Fig. 1) adjacent to the control-source electrode plate; and a second semiconductor region (e.g., Chen, second semiconductor region of 1 adjacent to 3, Fig. 1) adjacent to the drain electrode, wherein the first semiconductor region and the second semiconductor region are of a same conductivity type (e.g., Chen, p-type, Fig. 1).
Regarding claim 8, Chen in view of Li teaches the semiconductor device of claim 1, wherein the control-source electrode plate entirely overlaps the gate structure along the direction (e.g., Li, Fig. 1B).
Regarding claim 9, Chen in view of Li teaches the semiconductor device of claim 1, wherein the control-source electrode plate further extends beyond a sidewall of the gate structure (e.g., Li, Fig. 1B).
Allowable Subject Matter
Claims 5-7 and 10-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 17 is allowed at this time, pending updated search before the Examiner's next response, because the prior art of record neither anticipates nor render obvious the limitation of claim 17 that recites “a charge-enhanced oxide layer between the control-source electrode plate and the semiconductor layer” in combination with other elements of claim 17.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bo Bin Jang whose telephone number is (571) 270-0271. The examiner can normally be reached on M-F from 9:00 AM to 6:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BO B JANG/Primary Examiner, Art Unit 2818 June 18, 2026
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