DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/27/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5 & 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Khlat et al. (US 8,493,141 B2, hereinafter Khlat).
Regarding claims 1 & 11:
Khlat discloses in Fig. 2A, a power amplifier circuit comprising:
a power amplifier (amplifier 22) configured to amplify a radio-frequency signal;
a supply voltage terminal (e.g. terminal Vcc) coupled to the power amplifier via a supply voltage path (see a path include node 28) that provides a supply voltage supplied at the supply voltage terminal to the power amplifier; and
a first bypass capacitor (bypass capacitor 19) coupled between a ground and the supply voltage path, wherein:
a first supply voltage (voltage at node 26) to be supplied to the supply voltage terminal is configured in a digital envelope tracking mode (see Col. 1, lines 16-18, envelope tracker in a power management system of mobile communications equipment), that tracks the radio-frequency signal and varies across a plurality of discrete voltage levels (multiple level, see element 56) within a single frame of the radio-frequency signal and (Claim 11) wherein a supply voltage terminal coupled to a digital envelope tracker (power management system 10A of Fig. 2A) except for the first bypass capacitor (capacitor 19) has a first electrostatic capacity equal to or higher than a value that is determined to cause the power amplifier circuit with the first supply voltage being provided to the supply voltage terminal to have a higher efficiency than a threshold efficiency.
Khlat discloses, Col. 5, lines 55-63, the estimated bypass capacitor capacitance parameter, C_BYPASS, may be either the measured or estimate capacitance of the bypass capacitor, C.sub.BYPASS, 19 measured between a specific range of frequencies. For example, the estimated bypass capacitor capacitance parameter, C_BYPASS, may be either the measured or estimated capacitance of the bypass capacitor, C_BYPASS, 19 between approximately 10 MHz and 30 MHz.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to have set, selected or characterized the first bypass capacitor has a first electrostatic capacity equal to or higher than a value that is determined to cause the power amplifier circuit with the first supply voltage being provided to the supply voltage terminal to have a higher efficiency than a threshold efficiency, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art.
Regarding claim 2 & 12:
Khlat discloses the power amplifier circuit according to claim 1, wherein the threshold efficiency corresponds to an efficiency of the power amplifier circuit in an average power tracking mode ( see Col. 16, The boost time counter 186 may be used to keep track of the time that the multi-level charge pump buck converter 12 of FIG. 2A is in either the first boost output mode or the second output boost mode. When the multi-level charge pump buck converter 12 is in either the first boost output mode or the second boost output mode and (see Col. 12, lines 16-28, based upon the shunt level threshold parameter, the series level threshold parameter, the first boost level threshold parameter, and the second boost level threshold parameter, the programmable threshold circuit 122 generates a shunt level threshold 124, a series level threshold 126, a first boost level threshold 128, and a second boost level threshold 130, respectively, which is provided to the threshold detector and control circuit 132A. In those embodiments that provide for a first output threshold parameter and a first output mode of operation of the multi-level charge pump circuit 56, the programmable threshold circuit 122 may further generate a first output threshold (not shown), which is provided to the threshold detector and control circuit 132A).
Regarding claims 3-5 & 13-15:
Khlat discloses the limitations as applied in claim 1 except for wherein the first bypass capacitor has the first electrostatic capacity equal to or higher than 5 nanofarads; and wherein the first bypass capacitor has the first electrostatic capacity equal to or lower than 20 nanofarads; and wherein the first bypass capacitor has the first electrostatic capacity equal to or lower than 10 nanofarads.
Khlat further discloses in Col. 45, lines 43-45, an estimated bypass capacitor capacitance parameter, C_BYPASS, and an estimated power amplifier transconductance parameter; and in Col. 45, lines 55-63.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to have selected to chosen the first electrostatic capacity equal to or higher than 5 nanofarads; and/or the first electrostatic capacity equal to or lower than 20 nanofarads; and/or the first electrostatic capacity equal to or lower than 10 nanofarads since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art.
Allowable Subject Matter
Claims 6-10 & 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 6-10 & 16-20 are allowable since the closest prior art (i.e., Khlat) as discussed above does not disclose further comprising: a first switch coupled between the supply voltage path and the first bypass capacitor; and a second bypass capacitor coupled between the ground and the supply voltage path, the second bypass capacitor having a second electrostatic capacity that is lower than the first electrostatic capacity of the first bypass capacitor.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)270-3941. The examiner can normally be reached Mon-Fri 8:00 AM-5:00 PM EST.
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/KHIEM D NGUYEN/Examiner, Art Unit 2843
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