Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/20/2024 and 9/29/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 8, 15, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Galatage (US 20230402507 A1).
Regarding claim 1, Galatage discloses a semiconductor device (Fig. 1A) comprising:
a first nanodevice (100c) including a plurality of first upper transistors (101) and a plurality of first lower transistors (140), wherein the first nanodevice includes a first upper source/drain (105a) and a first lower source/drain (105c);
a shared source/drain contact (118a/118c) extending through (completely through) the first upper source/drain and the first lower source/drain; and
an isolation interlayer dielectric (ILD) (150/102) in direct contact (direct contact is shown) with at least one surface (a portion of the surface) of the shared source/drain contact.
Illustrated below is a marked and annotated figure of Fig. 1A of Galatage.
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Regarding independent claim 8, Galatage discloses a semiconductor device (Fig. 1A) comprising:
a first nanodevice (100c) including a plurality of first upper transistors (101) and a plurality of first lower transistors (140), wherein the first nanodevice includes a first upper source/drain (105a), a second upper source/drain (105b), a first lower source/drain (105c), and a second lower source/drain (105d);
a shared source/drain contact (118a/118c) extending through (completely through) the first upper source/drain and the first lower source/drain;
a first independent source/drain contact (118b) extending upwards through (completely through) the second upper source/drain and a first independent backside source/drain contact (118d) extending downwards through (completely through) the second lower source/drain; and
an isolation ILD (150/102) in direct contact (direct contact is shown) with at least one surface (a portion of the surface) of the shared source/drain contact.
Regarding independent claim 15, Galatage discloses a semiconductor device (Fig. 1A) comprising:
a first nanodevice (100c) including a plurality of first upper transistors (101) and a plurality of first lower transistors (140), wherein the first nanodevice includes a first upper source/drain (105a), a second upper source/drain (105b), a first lower source/drain (105c), and a second lower source/drain (105d);
a second nanodevice ([0095]: “may include one or more integrated circuit structures or devices formed using the disclosed techniques” teaches duplication of parts. Note: a duplicate of nanodevice 100c is relied upon here as “a second nanodevice”) including a plurality of second upper transistors (101) and a plurality of second lower transistors (140), wherein the second nanodevice is located adjacent to and parallel to the first nanodevice (duplicated 100c would be formed in the same way as the original 100c, and thus it must necessarily be “adjacent to and parallel to”), wherein the second nanodevice includes a third upper source/drain (105b) and a third lower source/drain (105d);
a shared source/drain contact (118a/118c) extending through (completely through) the first upper source/drain and the first lower source/drain;
a first independent source/drain contact (118b) extending upwards through (completely through) the second upper source/drain, a second independent source/drain contact (118b of duplicated 100c) extending upwards through (completely through) the third upper source/drain, a first independent backside source/drain contact (118d) extending downwards through (completely through) the second lower source/drain, and a second independent backside source/drain contact (118d of duplicated 100c) extending downwards through (completely through) the third lower source/drain; and
an isolation ILD (150/102) in direct contact (direct contact is shown) with at least one surface (a portion of the surface) of the shared source/drain contact.
Regarding claim 19, Galatage discloses the semiconductor device of claim 15 (Fig. 1A), wherein the shared source/drain contact extends a first height (Z height of 101+140, See dashed reference lines for height measurement endpoints) perpendicular to a y-axis (See annotated figure for axis designation), wherein the first independent source/drain contact and the first independent backside source/drain contact each extend a second height (Z height of 101 or 140, See dashed reference lines for height measurement endpoints) perpendicular to the y-axis, and wherein the first height is greater than the second height (“greater than” because the 1st height fully includes at least each of the 2nd heights).
Regarding claim 20, Galatage discloses the semiconductor device of claim 19 (Fig. 1A), further comprising:
a frontside silicide liner (135a; [0037]: “silicide”) located along a first portion (118a) of sidewalls of the shared source/drain contact where the shared source/drain contact passes through (completely through) the first upper source/drain; and
a backside silicide liner (135c; [0037]: “silicide”) located along a second portion (118c) of the sidewalls of the shared source/drain contact where the shared source/drain contact passes through (completely through) the first lower source/drain, wherein the frontside silicide liner and the backside silicide liner are comprised of a different material ([0037]: “a second metal different from the first metal”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference (or combination of references), but are disclosed or rendered obvious by secondary references or remarks.
Claims 2-7 are rejected under 35 U.S.C. 103 as being unpatentable over Galatage as applied to claim 1 above, and further in view of Wang (US 20250006741 A1).
Regarding claim 2, Galatage discloses the semiconductor device of claim 1, but fails to teach isolation ILD or their associated interconnection wirings connected to the semiconductor device. Thus, Galatage fails to teach “wherein the isolation ILD includes a frontside isolation ILD in direct contact with a frontside surface of the shared source/drain contact”.
Wang discloses isolation ILD and their associated interconnection wirings (Fig. 18B) connected to the semiconductor device,
wherein the isolation ILD includes a frontside isolation ILD (332/334, See annotated figure) in direct contact with a frontside surface of the shared source/drain contact (See annotated figure for surface designation).
Modifying the semiconductor device of Galatage by including the isolation ILD configuration of Wang would arrive at the claimed isolation ILD configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the semiconductor device includes source drain contacts (Galatage: contacts 118a-d; Wang: contacts 310/310`/390) for stacked transistors (Galatage: transistors 101/140; Wang: [0099]: “transistor”). Wang provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the isolation ILD configuration in that it would enable interconnecting the contacts with other circuitry within the semiconductor device ([0107]: “electrically connecting”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed isolation ILD configuration because it would enable interconnecting the contacts with other circuitry within the semiconductor device. MPEP 2143 (I)(G).
Illustrated below is a marked and annotated figure of Fig. 18B of Wang.
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Regarding claim 3, Galatage in view of Wang discloses the semiconductor device of claim 2 (Wang: Fig. 18B), further comprising:
a back-end-of-line (BEOL) layer (354) in direct contact (direct contact is shown) with a frontside surface of the frontside isolation ILD (See annotated figure for surface designation).
Regarding claim 4, Galatage discloses the semiconductor device of claim 1, but fails to teach isolation ILD or their associated interconnection wirings connected to the semiconductor device. Thus, Galatage fails to teach “wherein the isolation ILD includes a backside isolation ILD in direct contact with a backside surface of the shared source/drain contact”.
Wang discloses isolation ILD and their associated interconnection wirings (Fig. 18B) connected to the semiconductor device,
wherein the isolation ILD includes a backside isolation ILD (402/404, See annotated figure) in direct contact with a backside surface of the shared source/drain contact (See annotated figure for surface designation).
Modifying the semiconductor device of Galatage by including the isolation ILD configuration of Wang would arrive at the claimed isolation ILD configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the semiconductor device includes source drain contacts (Galatage: contacts 118a-d; Wang: contacts 310/310`/390) for stacked transistors (Galatage: transistors 101/140; Wang: [0099]: “transistor”). Wang provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the isolation ILD configuration in that it would enable interconnecting the contacts with other circuitry within the semiconductor device ([0107]: “electrically connecting”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed isolation ILD configuration because it would enable interconnecting the contacts with other circuitry within the semiconductor device. MPEP 2143 (I)(G).
Regarding claim 5, Galatage in view of Wang discloses the semiconductor device of claim 4 (Wang: Fig. 18B), further comprising:
a backside interconnect (Fig. 23B: 434) in direct contact (direct contact is shown) with a backside surface of the backside isolation ILD (backside isolation ILD is shown in phantom).
Regarding claim 6, Galatage discloses the semiconductor device of claim 1, but fails to teach isolation ILD or their associated interconnection wirings connected to the semiconductor device. Thus, Galatage fails to teach “wherein the isolation ILD includes a frontside isolation ILD in direct contact with a frontside surface of the shared source/drain contact and a backside isolation ILD in direct contact with a backside surface of the shared source/drain contact”.
Wang discloses isolation ILD and their associated interconnection wirings (Fig. 18B) connected to the semiconductor device,
wherein the isolation ILD includes a frontside isolation ILD (332/334, See annotated figure) in direct contact with a frontside surface of the shared source/drain contact (See annotated figure for surface designation) and a backside isolation ILD (402/404, See annotated figure) in direct contact with a backside surface of the shared source/drain contact (See annotated figure for surface designation).
Modifying the semiconductor device of Galatage by including the isolation ILD configuration of Wang would arrive at the claimed isolation ILD configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the semiconductor device includes source drain contacts (Galatage: contacts 118a-d; Wang: contacts 310/310`/390) for stacked transistors (Galatage: transistors 101/140; Wang: [0099]: “transistor”). Wang provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the isolation ILD configuration in that it would enable interconnecting the contacts with other circuitry within the semiconductor device ([0107]: “electrically connecting”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed isolation ILD configuration because it would enable interconnecting the contacts with other circuitry within the semiconductor device. MPEP 2143 (I)(G).
Regarding claim 7, Galatage in view of Wang discloses the semiconductor device of claim 6 (Wang: Fig. 18B), further comprising:
a BEOL layer (354) in direct contact (direct contact is shown) with a frontside surface of the frontside isolation ILD (See annotated figure for surface designation); and
a backside interconnect (Fig. 23B: 434) in direct contact (direct contact is shown) with a backside surface of the backside isolation ILD (backside isolation ILD is shown in phantom).
Claims 9-14 are rejected under 35 U.S.C. 103 as being unpatentable over Galatage as applied to claim 8 above, and further in view of Wang.
Regarding claim 9, Galatage discloses the semiconductor device of claim 8, but fails to teach isolation ILD or their associated interconnection wirings connected to the semiconductor device. Thus, Galatage fails to teach “wherein the isolation ILD includes a frontside isolation ILD in direct contact with a frontside surface of the shared source/drain contact”.
Wang discloses isolation ILD and their associated interconnection wirings (Fig. 18B) connected to the semiconductor device,
wherein the isolation ILD includes a frontside isolation ILD (332/334, See annotated figure) in direct contact with a frontside surface of the shared source/drain contact (See annotated figure for surface designation).
Modifying the semiconductor device of Galatage by including the isolation ILD configuration of Wang would arrive at the claimed isolation ILD configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the semiconductor device includes source drain contacts (Galatage: contacts 118a-d; Wang: contacts 310/310`/390) for stacked transistors (Galatage: transistors 101/140; Wang: [0099]: “transistor”). Wang provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the isolation ILD configuration in that it would enable interconnecting the contacts with other circuitry within the semiconductor device ([0107]: “electrically connecting”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed isolation ILD configuration because it would enable interconnecting the contacts with other circuitry within the semiconductor device. MPEP 2143 (I)(G).
Regarding claim 10, Galatage in view of Wang discloses the semiconductor device of claim 9 (Wang: Fig. 18B), further comprising:
a BEOL layer (354) in direct contact (direct contact is shown) with a frontside surface of the frontside isolation ILD (See annotated figure for surface designation) and a frontside surface of the first independent source/drain contact (See annotated figure for surface designation, “direct contact” is shown at least by point contact).
Regarding claim 11, Galatage discloses the semiconductor device of claim 8, but fails to teach isolation ILD or their associated interconnection wirings connected to the semiconductor device. Thus, Galatage fails to teach “wherein the isolation ILD includes a backside isolation ILD in direct contact with a backside surface of the shared source/drain contact”.
Wang discloses isolation ILD and their associated interconnection wirings (Fig. 18B) connected to the semiconductor device,
wherein the isolation ILD includes a backside isolation ILD (402/404, See annotated figure) in direct contact with a backside surface of the shared source/drain contact (See annotated figure for surface designation).
Modifying the semiconductor device of Galatage by including the isolation ILD configuration of Wang would arrive at the claimed isolation ILD configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the semiconductor device includes source drain contacts (Galatage: contacts 118a-d; Wang: contacts 310/310`/390) for stacked transistors (Galatage: transistors 101/140; Wang: [0099]: “transistor”). Wang provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the isolation ILD configuration in that it would enable interconnecting the contacts with other circuitry within the semiconductor device ([0107]: “electrically connecting”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed isolation ILD configuration because it would enable interconnecting the contacts with other circuitry within the semiconductor device. MPEP 2143 (I)(G).
Regarding claim 12, Galatage in view of Wang discloses the semiconductor device of claim 11 (Wang: Fig. 18B), further comprising:
a backside interconnect (Fig. 23B: 434) in direct contact (direct contact is shown) with a backside surface of the backside isolation ILD (backside isolation ILD is shown in phantom) and a backside surface of the first independent backside source/drain contact (See annotated figure for surface designation).
Regarding claim 13, Galatage discloses the semiconductor device of claim 8, but fails to teach isolation ILD or their associated interconnection wirings connected to the semiconductor device. Thus, Galatage fails to teach “wherein the isolation ILD includes a frontside isolation ILD in direct contact with a frontside surface of the shared source/drain contact and a backside isolation ILD in direct contact with a backside surface of the shared source/drain contact”.
Wang discloses isolation ILD and their associated interconnection wirings (Fig. 18B) connected to the semiconductor device,
wherein the isolation ILD includes a frontside isolation ILD (332/334, See annotated figure) in direct contact with a frontside surface of the shared source/drain contact (See annotated figure for surface designation) and a backside isolation ILD (402/404, See annotated figure) in direct contact with a backside surface of the shared source/drain contact (See annotated figure for surface designation).
Modifying the semiconductor device of Galatage by including the isolation ILD configuration of Wang would arrive at the claimed isolation ILD configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the semiconductor device includes source drain contacts (Galatage: contacts 118a-d; Wang: contacts 310/310`/390) for stacked transistors (Galatage: transistors 101/140; Wang: [0099]: “transistor”). Wang provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the isolation ILD configuration in that it would enable interconnecting the contacts with other circuitry within the semiconductor device ([0107]: “electrically connecting”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed isolation ILD configuration because it would enable interconnecting the contacts with other circuitry within the semiconductor device. MPEP 2143 (I)(G).
Regarding claim 14, Galatage in view of Wang discloses the semiconductor device of claim 13 (Wang: Fig. 18B), further comprising:
a BEOL layer (354) in direct contact (direct contact is shown) with a frontside surface of the frontside isolation ILD (See annotated figure for surface designation) and a frontside surface of the first independent source/drain contact (See annotated figure for surface designation, “direct contact” is shown at least by point contact); and
a backside interconnect (Fig. 23B: 434) in direct contact (direct contact is shown) with a backside surface of the backside isolation ILD (backside isolation ILD is shown in phantom) and a backside surface of the first independent backside source/drain contact (See annotated figure for surface designation).
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Galatage as applied to claim 15 above, and further in view of Wang.
Regarding claim 16, Galatage discloses the semiconductor device of claim 15, but fails to teach isolation ILD or their associated interconnection wirings connected to the semiconductor device. Thus, Galatage fails to teach
“wherein the isolation ILD includes a frontside isolation ILD in direct contact with a frontside surface of the shared source/drain contact, wherein the semiconductor device further comprises:
a BEOL layer in direct contact with a frontside surface of the frontside isolation ILD, a frontside surface of the first independent source/drain contact, and a frontside surface of the second independent source/drain contact”.
Wang discloses isolation ILD and their associated interconnection wirings (Fig. 18B) connected to the semiconductor device,
wherein the isolation ILD includes a frontside isolation ILD (332/334, See annotated figure) in direct contact with a frontside surface of the shared source/drain contact (See annotated figure for surface designation), wherein the semiconductor device further comprises:
a BEOL layer (354) in direct contact (direct contact is shown) with a frontside surface of the frontside isolation ILD (See annotated figure for surface designation), a frontside surface of the first independent source/drain contact (See annotated figure for surface designation, “direct contact” is shown at least by point contact), and a frontside surface of the second independent source/drain contact (with respect to the duplicated 100c, See annotated figure for surface designation, “direct contact” is shown at least by point contact).
Modifying the semiconductor device of Galatage by including the isolation ILD and BEOL layer configuration of Wang would arrive at the claimed isolation ILD and BEOL layer configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the semiconductor device includes source drain contacts (Galatage: contacts 118a-d; Wang: contacts 310/310`/390) for stacked transistors (Galatage: transistors 101/140; Wang: [0099]: “transistor”). Wang provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the isolation ILD and BEOL layer configuration in that it would enable interconnecting the contacts with other circuitry within the semiconductor device ([0107]: “electrically connecting”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed isolation ILD and BEOL layer configuration because it would enable interconnecting the contacts with other circuitry within the semiconductor device. MPEP 2143 (I)(G).
Regarding claim 17, Galatage discloses the semiconductor device of claim 15, but fails to teach isolation ILD or their associated interconnection wirings connected to the semiconductor device. Thus, Galatage fails to teach
“wherein the isolation ILD includes a backside isolation ILD in direct contact with a backside surface of the shared source/drain contact, wherein the semiconductor device further comprises:
a backside interconnect in direct contact with a backside surface of the backside isolation ILD, a backside surface of the first independent backside source/drain contact, and a backside surface of the second independent backside source/drain contact”.
Wang discloses isolation ILD and their associated interconnection wirings (Fig. 18B) connected to the semiconductor device,
wherein the isolation ILD includes a backside isolation ILD (402/404, See annotated figure) in direct contact with a backside surface of the shared source/drain contact (See annotated figure for surface designation), wherein the semiconductor device further comprises:
a backside interconnect (Fig. 23B: 434) in direct contact (direct contact is shown) with a backside surface of the backside isolation ILD (backside isolation ILD is shown in phantom), a backside surface of the first independent backside source/drain contact (See annotated figure for surface designation), and a backside surface of the second independent backside source/drain contact (with respect to the duplicated 100c, See annotated figure for surface designation).
Modifying the semiconductor device of Galatage by including the isolation ILD and backside interconnect configuration of Wang would arrive at the claimed isolation ILD and backside interconnect configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the semiconductor device includes source drain contacts (Galatage: contacts 118a-d; Wang: contacts 310/310`/390) for stacked transistors (Galatage: transistors 101/140; Wang: [0099]: “transistor”). Wang provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the isolation ILD and backside interconnect configuration in that it would enable interconnecting the contacts with other circuitry within the semiconductor device ([0107]: “electrically connecting”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed isolation ILD and backside interconnect configuration because it would enable interconnecting the contacts with other circuitry within the semiconductor device. MPEP 2143 (I)(G).
Regarding claim 18, Galatage discloses the semiconductor device of claim 15, but fails to teach isolation ILD or their associated interconnection wirings connected to the semiconductor device. Thus, Galatage fails to teach
“wherein the isolation ILD includes a frontside isolation ILD in direct contact with a frontside surface of the shared source/drain contact and a backside isolation ILD in direct contact with a backside surface of the shared source/drain contact, wherein the semiconductor device further comprises:
a BEOL layer in direct contact with a frontside surface of the frontside isolation ILD, a frontside surface of the first independent source/drain contact, and a frontside surface of the second independent source/drain contact; and
a backside interconnect in direct contact with a backside surface of the backside isolation ILD, a backside surface of the first independent backside source/drain contact, and a backside surface of the second independent backside source/drain contact”.
Wang discloses isolation ILD and their associated interconnection wirings (Fig. 18B) connected to the semiconductor device,
wherein the isolation ILD includes a frontside isolation ILD (332/334, See annotated figure) in direct contact with a frontside surface of the shared source/drain contact (See annotated figure for surface designation) and a backside isolation ILD (402/404, See annotated figure) in direct contact with a backside surface of the shared source/drain contact (See annotated figure for surface designation), wherein the semiconductor device further comprises:
a BEOL layer (354) in direct contact (direct contact is shown) with a frontside surface of the frontside isolation ILD (See annotated figure for surface designation), a frontside surface of the first independent source/drain contact (See annotated figure for surface designation, “direct contact” is shown at least by point contact), and a frontside surface of the second independent source/drain contact (with respect to the duplicated 100c, See annotated figure for surface designation, “direct contact” is shown at least by point contact); and
a backside interconnect (Fig. 23B: 434) in direct contact (direct contact is shown) with a backside surface of the backside isolation ILD (backside isolation ILD is shown in phantom), a backside surface of the first independent backside source/drain contact (See annotated figure for surface designation), and a backside surface of the second independent backside source/drain contact (with respect to the duplicated 100c, See annotated figure for surface designation).
Modifying the semiconductor device of Galatage by including the isolation ILD, BEOL layer, and backside interconnect configuration of Wang would arrive at the claimed isolation ILD, BEOL layer, and backside interconnect configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the semiconductor device includes source drain contacts (Galatage: contacts 118a-d; Wang: contacts 310/310`/390) for stacked transistors (Galatage: transistors 101/140; Wang: [0099]: “transistor”). Wang provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the isolation ILD, BEOL layer, and backside interconnect configuration in that it would enable interconnecting the contacts with other circuitry within the semiconductor device ([0107]: “electrically connecting”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed isolation ILD, BEOL layer, and backside interconnect configuration because it would enable interconnecting the contacts with other circuitry within the semiconductor device. MPEP 2143 (I)(G).
Conclusion
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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