Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
All claims receive the priority date of May 20, 2024 because features identifiable pattern is symmetric about only one axis presented in all independent claims, claims 1, 7, and 14, are not disclosed in the parent application.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4,7-11,14-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matsumura et al (PG Pub 2010/0328917 A1).
Regarding claim 1, Matsumura teaches a semiconductor device, comprising: a plurality of first interconnect pads (43 or 45/24, figs. 11,14,15) formed over a surface of a semiconductor die (21 and/or 16, fig. 11); and a plurality of second interconnect pads (45/24 or 43) formed over the surface of the semiconductor die, wherein the second interconnect pads have an area different from an area (paragraph [0042]) of the first interconnect pads, and the first interconnect pads and second interconnect pads are electrically common (connected together by wires 51) and arranged in an identifiable pattern for alignment (fig. 14: the pads are identifiable and thus can be used for alignment) where the identifiable pattern is symmetric about only one axis (paragraph [0045]) that is substantially parallel with a side (top or bottom side) of the semiconductor die.
Regarding claim 2, Matsumura teaches the semiconductor device of claim 1, wherein the identifiable pattern includes rows (figs. 14 and 15) of the first interconnect pads.
Regarding claim 3, Matsumura teaches the semiconductor device of claim 1, wherein the identifiable pattern includes alternating offset ones of the first interconnect pads (figs. 14 and 15).
Regarding claim 4, Matsumura teaches the semiconductor device of claim 1, wherein the identifiable pattern includes the first interconnect pads interposed between the second interconnect pads (figs. 14 and 15).
Regarding claim 7, Matsumura teaches (see claim 1) a semiconductor device, comprising: a semiconductor die; and a plurality of interconnect pads formed over a surface of the semiconductor die, wherein first ones of the plurality of interconnect pads have an area different from an area of second ones of the plurality of interconnect pads forming an identifiable pattern symmetric about only one axis that is substantially parallel with a side of the semiconductor die.
Regarding claim 8, Matsumura teaches the semiconductor device of claim 7, wherein the plurality of interconnect pads are electrically common (connected together by wires 51).
Regarding claim 9, Matsumura teaches the semiconductor device of claim 7, wherein the identifiable pattern includes rows of the plurality of interconnect pads (figs. 14 and 15).
Regarding claim 10, Matsumura teaches the semiconductor device of claim 7, wherein the identifiable pattern includes alternating offset ones of the plurality of interconnect pads (figs. 14 and 15).
Regarding claim 11, Matsumura teaches the semiconductor device of claim 7, wherein the identifiable pattern includes the first ones of the plurality of interconnect pads interposed between the second ones of the plurality of interconnect pads (figs. 14 and 15).
Regarding claim 14, Matsumura teaches (see claim 1) a method of making a semiconductor device, comprising: providing a semiconductor die; forming a plurality of first interconnect pads over a surface of the semiconductor die; and forming an identifiable pattern, the identifiable pattern symmetric about only one axis that is substantially parallel with a side of the semiconductor die, through forming a plurality of second interconnect pads over the surface of the semiconductor die, wherein the second interconnect pads have an area different from an area of the first interconnect pads.
Regarding claim 15, Matsumura teaches the method of claim 14, wherein the first interconnect pads and second interconnect pads are electrically common (connected by wires 51).
Regarding claim 16, Matsumura teaches the method of claim 14, wherein the identifiable pattern includes rows of the first interconnect pads (figs. 14 and 15).
Regarding claim 17, Matsumura teaches the method of claim 14, wherein the identifiable pattern includes alternating offset ones of the first interconnect pads (figs. 14 and 15).
Regarding claim 18, Matsumura teaches the method of claim 14, wherein the identifiable pattern includes the first interconnect pads interposed between the second interconnect pads (figs. 14 and 15).
Claim(s) 7,9,12,14,16,19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Burbidge et al (PG Pub 2012/0175688 A1).
Regarding claim 7, Burbidge teaches a semiconductor device, comprising: a semiconductor die (fig. 2D); and a plurality of interconnect pads formed over a surface of the semiconductor die, wherein first ones of the plurality of interconnect pads (224a, 224b, including or excluding 220) have an area different (paragraph [0030]) from an area of second ones of the plurality of interconnect pads (224c to 224e) forming an identifiable pattern symmetric about only one axis (paragraph [0030]) that is substantially parallel with a side of the semiconductor die.
Regarding claim 9, Burbidge teaches the semiconductor device of claim 7, wherein the identifiable pattern includes rows of the plurality of interconnect pads (fig. 2D).
Regarding claim 12, Burbidge teaches the semiconductor device of claim 7, further including a transistor (paragraph [0010]) formed within the semiconductor die.
Regarding claim 14, Burbidge teaches (see claim 7) a method of making a semiconductor device, comprising: providing a semiconductor die; forming a plurality of first interconnect pads over a surface of the semiconductor die; and forming an identifiable pattern, the identifiable pattern symmetric about only one axis that is substantially parallel with a side of the semiconductor die, through forming a plurality of second interconnect pads over the surface of the semiconductor die, wherein the second interconnect pads have an area different from an area of the first interconnect pads.
Regarding claim 16, Burbidge teaches the method of claim 14, wherein the identifiable pattern includes rows of the first interconnect pads (fig. 2D).
Regarding claim 19, Burbidge teaches the method of claim 14, further including forming a transistor (paragraph [0010]) within the semiconductor die.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1,2,5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Burbidge et al (PG Pub 2012/0175688 A1) and Suzuki et al (PG Pub 2013/0320454 A1).
Regarding claim 1, Burbidge teaches (see claim 7) a semiconductor device, comprising: a plurality of first interconnect pads formed over a surface of a semiconductor die; and a plurality of second interconnect pads formed over the surface of the semiconductor die, wherein the second interconnect pads have an area different from an area of the first interconnect pads, and the first interconnect pads and second interconnect pads are arranged in an identifiable pattern for alignment (fig. 2D: the pads are identifiable and thus can be used for alignment) where the identifiable pattern is symmetric about only one axis that is substantially parallel with a side of the semiconductor die.
Burbidge does not teach the first interconnect pads and second interconnect pads are electrically common.
In the same field of endeavor, Suzuki teaches to connect all source pads to the same potential, for the benefit of achieving ease of wiring manufacturing (paragraph [0094]).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make the first interconnect pads and second interconnect pads to be electrically common, for the benefit of achieving ease of wiring manufacturing.
Regarding claim 2, Burbidge teaches the semiconductor device of claim 1, wherein the identifiable pattern includes rows (fig. 2D) of the first interconnect pads.
Regarding claim 5, Burbidge teaches the semiconductor device of claim 1, further including a transistor (paragraph [0010]) formed within the semiconductor die.
Claim(s) 8 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Burbidge et al (PG Pub 2012/0175688 A1) as applied to claims 7 and 14 above, and further in view of Suzuki et al (PG Pub 2013/0320454 A1).
Regarding claim 8, Burbidge remains as applied in claim 7.
Burbidge does not teach the plurality of interconnect pads are electrically common.
In the same field of endeavor, Suzuki teaches to connect all source pads to the same potential, for the benefit of achieving ease of wiring manufacturing (paragraph [0094]).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make the plurality of interconnect pads to be electrically common, for the benefit of achieving ease of wiring manufacturing.
Regarding claim 15, Burbidge remains as applied in claim 14.
Burbidge does not teach the first interconnect pads and second interconnect pads are electrically common.
In the same field of endeavor, Suzuki teaches to connect all source pads to the same potential, for the benefit of achieving ease of wiring manufacturing (paragraph [0094]).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make the first interconnect pads and second interconnect pads to be electrically common, for the benefit of achieving ease of wiring manufacturing.
Claim(s) 6,13,20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsumura et al (PG Pub 2010/0328917 A1) as applied to claims 1,7,14 above, and further in view of Feng et al (PG Pub 2012/0104580 A1).
Regarding claim 6, Matsumura remains as applied in claim 1.
Matsumura does not teach a plurality of bumps formed over the first interconnect pads and second interconnect pads.
In the same field of endeavor, Feng teaches a plurality of bumps (1213 and 1212, figs. 14A and 14B) formed over the first interconnect pad (1408) and second interconnect pad (1406), for the benefit of electrically connecting the device to external elements (paragraph [0039]), such as power source.
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to form a plurality of bumps over the first interconnect pads and second interconnect pads for the benefit of electrically connecting the device to external elements, such as power source.
Regarding claim 13, Matsumura remains as applied in claim 7.
Matsumura does not teach a plurality of bumps formed over the plurality of interconnect pads.
In the same field of endeavor, Feng teaches a plurality of bumps (1213 and 1212, figs. 14A and 14B) formed over the plurality of interconnect pads (1408 and 1406), for the benefit of electrically connecting the device to external elements (paragraph [0039]), such as power source.
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to form a plurality of bumps over the plurality of interconnect pads for the benefit of electrically connecting the device to external elements, such as power source.
Regarding claim 20, Matsumura remains as applied in claim 14.
Matsumura does not teach a plurality of bumps formed over the first interconnect pads and second interconnect pads.
In the same field of endeavor, Feng teaches a plurality of bumps (1213 and 1212, figs. 14A and 14B) formed over the first interconnect pad (1408) and second interconnect pad (1406), for the benefit of electrically connecting the device to external elements (paragraph [0039]), such as power source.
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to form a plurality of bumps over the first interconnect pads and second interconnect pads for the benefit of electrically connecting the device to external elements, such as power source.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Burbidge et al (PG Pub 2012/0175688 A1) and Suzuki et al (PG Pub 2013/0320454 A1) as applied to claim 1 above, and further in view of Feng et al (PG Pub 2012/0104580 A1).
Regarding claim 6, the previous combination remains as applied in claim 1.
The previous combination does not teach a plurality of bumps formed over the first interconnect pads and second interconnect pads.
In the same field of endeavor, Feng teaches a plurality of bumps (1213 and 1212, figs. 14A and 14B) formed over the first interconnect pad (1408) and second interconnect pad (1406), for the benefit of electrically connecting the device to external elements (paragraph [0039]), such as power source.
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to form a plurality of bumps over the first interconnect pads and second interconnect pads for the benefit of electrically connecting the device to external elements, such as power source.
Claim(s) 13 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Burbidge et al (PG Pub 2012/0175688 A1) as applied to claims 7 and 14 above, and further in view of Feng et al (PG Pub 2012/0104580 A1).
Regarding claim 13, Burbidge remains as applied in claim 7.
Burbidge does not teach a plurality of bumps formed over the plurality of interconnect pads.
In the same field of endeavor, Feng teaches a plurality of bumps (1213 and 1212, figs. 14A and 14B) formed over the plurality of interconnect pads (1408 and 1406), for the benefit of electrically connecting the device to external elements (paragraph [0039]), such as power source.
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to form a plurality of bumps over the plurality of interconnect pads for the benefit of electrically connecting the device to external elements, such as power source.
Regarding claim 20, Burbidge remains as applied in claim 14.
Burbidge does not teach a plurality of bumps formed over the first interconnect pads and second interconnect pads.
In the same field of endeavor, Feng teaches a plurality of bumps (1213 and 1212, figs. 14A and 14B) formed over the first interconnect pad (1408) and second interconnect pad (1406), for the benefit of electrically connecting the device to external elements (paragraph [0039]), such as power source.
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to form a plurality of bumps over the first interconnect pads and second interconnect pads for the benefit of electrically connecting the device to external elements, such as power source.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsumura et al (PG Pub 2010/0328917 A1) as applied to claim 1 above, and further in view of Hosomi (PG Pub 2001/0028114 A1).
Regarding claim 5, Matsumura remains as applied in claim 1.
Matsumura does not teach a transistor (paragraph [0010]) formed within the semiconductor die.
In the same field of endeavor, Hosomi teaches a transistor can activate memory cells (paragraph [0149]).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to form a transistor within the semiconductor die, for the benefit of activating the memory cells in the device in fig. 1 in which the device in fig. 2 is formed (paragraphs [0024][0025]).
Conclusion
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/FEIFEI YEUNG LOPEZ/Primary Examiner, Art Unit 2899
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