Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Abstract
The abstract of the disclosure is objected to because it is written in legal terminology which is too similar to claim language. In particular, legal phraseology such as the term “comprising”, “said” and “wherein” which are commonly used to define the limitations and scope pf patent claims, should generally be avoided in U.S. patent abstracts because the purpose of the abstract is not to define the patent claims, but to provide the reader with a clear and concise summary. The abstract should use plain language to describe the invention's technical problem, solution, and principal use. The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” etc. Correction is required. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6-8, 10, 12-15 and 18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Park et al. (US 20250040242).
Regarding claim 1. Fig 1B of Park discloses A semiconductor device 10 comprising:
a first nanosheet transistor structure ([0034]: the lower transistor with 110);
a second nanosheet transistor structure ([0034]: the upper transistor with 120) stacked on the first nanosheet transistor structure;
a semiconductor layer 140 [0043] disposed between the first nanosheet transistor structure and the second nanosheet transistor structure;
a first dielectric spacer 116 ([0056]: the left 116 around the left end of 140) disposed around a first end portion (left end portion) of the semiconductor layer; and
a second dielectric spacer 116 ([0056]: the right 116 around the right end of 140) disposed around a second end portion (right end portion of 140) of the semiconductor layer,
wherein the second end portion of the semiconductor layer is disposed opposite the first end portion (Fig 1B).
Regarding claim 2. Park discloses The semiconductor device of claim 1, wherein the first end portion and the second end portion of the semiconductor layer respectively connect an upper surface of the semiconductor layer with a lower surface of the semiconductor layer (Fig 1B).
Regarding claim 3. Park discloses The semiconductor device of claim 1, wherein:
a part of the first dielectric spacer is disposed over a first surface (top surface) of the semiconductor layer and another part of the first dielectric spacer is disposed under a second surface (bottom surface) of the semiconductor layer (Fig 1B);
a part of the second dielectric spacer is disposed over the first surface of the semiconductor layer and another part of the second dielectric spacer is disposed under the second surface of the semiconductor layer (Fig 1B).
Regarding claim 6. Park discloses The semiconductor device of claim 1, further comprising:
a first gate structure 115 [0034] corresponding to the first nanosheet transistor structure formed on a first surface (the lower surface of 140) of the semiconductor layer (Fig 1B); and
a second gate structure 125 [0034] corresponding to the second nanosheet transistor structure formed on a second surface of the semiconductor layer (Fig 1B);
wherein the second surface is opposite the first surface (Fig 1B: top vs bottom surfaces).
Regarding claim 7. Park discloses The semiconductor device of claim 6, wherein portions of the first dielectric spacer and of the second dielectric spacer are formed on sides of the first gate structure and of the second gate structure (Fig 1B).
Regarding claim 8. Park discloses The semiconductor device of claim 1, wherein:
the first nanosheet transistor structure comprises a first plurality of gate structures 115 alternately stacked with a first plurality of channel layers 112;
the second nanosheet transistor structure comprises a second plurality of gate structures 125 alternately stacked with a second plurality of channel layers 122; and
the first and second dielectric spacers and the semiconductor layer are disposed between a first channel layer of the first plurality of channel layers and a second channel layer of the second plurality of channel layers (Fig 1B).
Regarding claim 10. Park discloses The semiconductor device of claim 1, further comprising at least one source/drain region 135/145 disposed on a side of at least one of the first nanosheet transistor structure and the second nanosheet transistor structure, wherein the semiconductor layer is electrically isolated from the at least one source/drain region (Fig 1B).
Regarding claim 12. Fig 1B of Park discloses A semiconductor device comprising:
a plurality of gate structures 115/125 alternately stacked with a plurality of channel layers 112/122,
wherein the plurality of channel layers contact at least one source/drain region 135/145 disposed on at least one side of the plurality of gate structures and the plurality of channel layers (Fig 1B);
a semiconductor layer 140 disposed between a first gate structure (the uppermost gate structure 115) and a second gate structure (the lowermost gate structure 125) of the plurality of gate structures; and
at least one dielectric spacer 116 disposed around at least one end portion of the semiconductor layer (Fig 1B);
wherein the semiconductor layer is electrically isolated from the at least one source/drain region (Fig 1B: via 116 adjacent to 140).
Regarding claim 13. Park discloses The semiconductor device of claim 12, wherein the at least one end portion of the semiconductor layer connects an upper surface of the semiconductor layer with a lower surface of the semiconductor layer (Fig 1B: see the 116 adjacent to 140).
Regarding claim 14. Park discloses The semiconductor device of claim 13, wherein the at least one dielectric spacer is disposed over a portion of the upper surface of the semiconductor layer and under a portion of the lower surface of the semiconductor layer (Fig 1B).
Regarding claim 15. Park discloses The semiconductor device of claim 12, wherein portions of the at least one dielectric spacer are formed on sides of the first gate structure and of the second gate structure (Fig 1B).
Regarding claim 18. Fig 1B of Park discloses A semiconductor device comprising:
a plurality of gate structures 115/125 stacked with a plurality of channel layers 112/122,
wherein the plurality of channel layers contact at least one source/drain region 135/145 disposed on at least one side of the plurality of gate structures and the plurality of channel layers;
wherein two or more gate structures of the plurality of gate structures are disposed between two adjacent channel layers of the plurality of channel layers (Fig 1B);
a dielectric spacer 116 disposed on sides of each of the two or more gate structures,
wherein the dielectric spacer (the 116 adjacent to 140) comprises a continuous structure from a first one (the uppermost gate structure 115) of the two or more gate structures to a last one (the lowermost gate structure 125) of the two or more gate structures (Fig 1B: the 116 adjacent 140 extends continuously from the side of the uppermost gate structure 115 to the side of the lowermost gate structure 125);
a semiconductor layer 140 disposed between each pair of adjacent gate structures of the two or more gate structures;
wherein the dielectric spacer is disposed on sides of each semiconductor layer and each semiconductor layer is electrically isolated from the at least one source/drain region (Fig 1B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20250040242).
Regarding claim 4. Park discloses The semiconductor device of claim 1. But Park does not explicitly disclose, wherein a thickness of the semiconductor layer is in a range of about 1 nm to about 5 nm.
However, Park discloses that middle isolation structure 140 is a silicon germanium (SiGe) layer having a relatively high germanium (Ge) concentration (e.g., about 55% Ge) epitaxially grown from an underlying SiGe layer having a relatively lower Ge concentration (e.g., about 25% Ge). Park further discloses that the Ge-rich SiGe layer cannot be grown above a critical thickness, because growth above the critical thickness may cause collapse of the first channel structure due to the material characteristics. Consequently, Park teaches that the thickness of the middle isolation structure is constrained by the critical thickness of the epitaxially grown Ge-rich SiGe layer.
Therefore, it was well understood by one of ordinary skill in the semiconductor fabrication art that the critical thickness of strained epitaxial SiGe layers is governed by lattice mismatch and is predicted by the Matthews-Blakeslee equilibrium critical thickness model. For a SiGe layer having approximately 55% Ge epitaxially grown on a SiGe layer having approximately 25% Ge, the equilibrium critical thickness is approximately 3.5 nm to 4.5 nm, which falls entirely within the claimed range.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select the thickness of Park's Ge-rich SiGe layer, and thus the corresponding middle isolation structure, to be within the claimed range of about 1 nm to about 5 nm, in order to maintain coherent epitaxial growth, suppress strain relaxation and misfit dislocations, prevent collapse of the first channel structure as expressly taught by Park, and thereby obtain the predictable benefit of maintaining structural integrity while providing electrical isolation. Selecting a thickness within the claimed range merely constitutes routine optimization of a known result-effective variable.
Furthermore, applicant's specification does not identify any criticality associated with the claimed thickness range of about 1 nm to about 5 nm, nor does it demonstrate that selecting a thickness within the claimed range achieves any unexpected result relative to thicknesses selected according to the known epitaxial critical-thickness constraint. Therefore, the claimed numerical range does not patentably distinguish over the prior art.
Regarding claim 5. Park discloses The semiconductor device of claim 4, wherein the thickness of the semiconductor layer is in a range of about 2 nm to about 3 nm.
As discussed above, Park expressly discloses that the thickness of the Ge-rich SiGe layer is limited by the critical thickness for epitaxial growth. The Matthews-Blakeslee equilibrium critical thickness model predicts a critical thickness of approximately 3.5 nm to 4.5 nm for the disclosed 55% Ge/25% Ge epitaxial system. One of ordinary skill in the art would have understood that, in practical semiconductor manufacturing, the epitaxial layer is ordinarily selected with a safety margin below the theoretical critical thickness to account for process variation, local strain fluctuations, and to ensure defect-free epitaxial growth.
Accordingly, it would have been obvious to select a thickness of about 2 nm to about 3 nm, which remains safely below the predicted critical thickness while predictably maintaining coherent epitaxial growth, preventing channel collapse, and providing sufficient electrical isolation. Such selection represents nothing more than routine optimization of a known result-effective variable using well-established epitaxial growth principles.
Moreover, applicant has not demonstrated that the narrower range of about 2 nm to about 3 nm is critical, nor has applicant shown that this narrower range achieves any unexpected result over other thicknesses below the known critical thickness. In the absence of evidence of criticality or unexpected results, selecting the claimed subrange would have been an obvious design choice to one of ordinary skill in the art.
Claims 9, 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20250040242) in view of Baek et al. (US 20230343823).
Regarding claim 9. Park discloses The semiconductor device of claim 8. But Park does not expressly disclose wherein a thickness of the semiconductor layer is less than thicknesses of respective ones of the first plurality of channel layers and of the second plurality of channel layers.
However, Baek discloses a semiconductor device including a semiconductor channel isolation layer 115C disposed between a lower channel structure 10L and an upper channel structure 10U. In particular, Fig. 5B illustrates semiconductor channel isolation layer 115C positioned between channel layers 110C and 120C. Baek further teaches that the channel isolation layer 115C is formed of a semiconductor material (e.g., silicon) ([0040]-[0044]).
Baek further teaches that the lower and upper channel layers 110C and 120C each have a thickness TH1 and TH2 of about 8 nm to 13 nm [0033], whereas the semiconductor channel isolation layer 115C has a thickness TH3 of about 2 nm [0042]. Accordingly, Baek teaches that the thickness of the semiconductor isolation layer 115C is less than the thicknesses of the respective channel layers 110C and 120C.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park's semiconductor layer to have a thickness less than the thicknesses of the adjacent channel layers as taught by Baek, in order to provide sufficient channel isolation while maintaining structural integrity during fabrication, improving etch selectivity during inner spacer formation, and preventing collapse of the channel structure, as recognized by Baek. Such modification merely involves selecting the relative thicknesses of known semiconductor layers to achieve their predictable and recognized functions.
Furthermore, applicant's specification does not identify any criticality associated with the claimed relative thickness relationship, nor does it demonstrate any unexpected result arising from making the semiconductor layer thinner than the adjacent channel layers. Accordingly, adopting the relative thickness relationship taught by Baek would have been an obvious design choice yielding predictable results.
Regarding claim 16. Baek discloses The semiconductor device of claim 12. But Park does not expressly disclose wherein a thickness of the semiconductor layer is less than thicknesses of respective ones of the plurality of channel layers.
However, Baek discloses a semiconductor device including a semiconductor isolation layer 115C disposed between lower channel layers 110C and upper channel layers 120C. In particular, Fig. 5B illustrates semiconductor isolation layer 115C positioned between channel layers 110C and 120C. Baek further teaches that the channel layers 110C and 120C each have thicknesses TH1 and TH2 of about 8 nm to 13 nm [0033], whereas semiconductor isolation layer 115C has a thickness TH3 of about 2 nm or less [0042]. Accordingly, Baek teaches that the thickness of semiconductor isolation layer 115C is less than the thicknesses of the respective channel layers 110C and 120C.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor layer of Park to have a thickness less than the thicknesses of the respective channel layers as taught by Baek in order to provide effective isolation between stacked channel structures while maintaining structural integrity during semiconductor fabrication. Such a relative thickness facilitates selective processing of the semiconductor isolation layer and formation of dielectric isolation structures while preserving the mechanical stability of the adjacent channel layers. The modification merely involves selecting a known relative thickness of semiconductor layers to achieve their recognized and predictable functions.
Furthermore, applicant's specification does not identify any criticality associated with the claimed relative thickness relationship, nor does it demonstrate any unexpected result arising from making the semiconductor layer thinner than the respective channel layers. Accordingly, adopting the relative thickness relationship taught by Baek would have been an obvious design choice yielding predictable results.
Regarding claim 19. Park discloses The semiconductor device of claim 18. But Park does not expressly disclose wherein a thickness of each semiconductor layer is less than thicknesses of respective ones of the plurality of channel layers.
However, Baek discloses a semiconductor device including a semiconductor isolation layer 115C disposed between lower channel layers 110C and upper channel layers 120C. In particular, Fig. 5B illustrates semiconductor isolation layer 115C positioned between channel layers 110C and 120C. Baek further teaches that channel layers 110C and 120C each have thicknesses TH1 and TH2 of about 8 nm to 13 nm [0033], whereas semiconductor isolation layer 115C has a thickness TH3 of about 2 nm or less [0042]. Accordingly, Baek teaches that the thickness of the semiconductor isolation layer is less than the thicknesses of the respective channel layers.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify each semiconductor layer of Park to have a thickness less than the thicknesses of the respective channel layers, as taught by Baek, in order to provide effective isolation between stacked channel structures while maintaining structural integrity during fabrication, facilitating selective processing of the semiconductor isolation layer, and improving formation of dielectric isolation structures. Such modification merely involves optimizing a known result-effective variable to obtain its recognized and predictable advantages.
Furthermore, applicant's specification does not identify any criticality associated with the claimed relative thickness relationship, nor does it demonstrate any unexpected result arising from making each semiconductor layer thinner than the respective channel layers. Accordingly, adopting the relative thickness relationship taught by Baek would have been an obvious design choice yielding predictable results.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20250040242) in view of Khaderbad (US 20230062940).
Regarding claim 11. Park discloses The semiconductor device of claim 1. But Park does not expressly disclose wherein at least a portion of the first dielectric spacer and of the second dielectric spacer comprises a rounded shape.
However, Fig 5 of Khaderbad discloses at least a portion (corner portions) of the first dielectric spacer 128 (left side of 134) and of the second dielectric spacer 128 (right side of 134) comprises a rounded shape (see enlarged view 501; along the topmost 122, 128 has rounded corner potion).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the dielectric spacers of Park to include the rounded corner portions taught by Khaderbad. A person of ordinary skill in the semiconductor fabrication art would have recognized that rounded dielectric spacer corners reduce stress concentration at dielectric corners, improve conformality of subsequently deposited dielectric and conductive films, reduce localized electric-field crowding, and improve process reliability during spacer formation and subsequent gate replacement processing. Such modification merely applies a known spacer geometry to obtain its recognized and predictable advantages without changing the basic operation of Park's semiconductor device. Furthermore, applicant's specification does not identify any criticality associated with the rounded corner geometry, nor does it demonstrate that providing rounded corner portions achieves any unexpected result compared with conventional rounded spacer geometries. Accordingly, adopting the rounded spacer configuration of Khaderbad in the semiconductor device of Park would have been an obvious design choice yielding predictable results.
Claims 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20250040242) in view of Ha et al. (US 20230052477).
Regarding claim 17. Baek discloses The semiconductor device of claim 12. But Park does not expressly disclose wherein a thickness of the first gate structure and a thickness of the second gate structure are less than thicknesses of remaining ones of the plurality of gate structures.
However, Ha discloses a semiconductor device including a plurality of gate structures having different thicknesses. Specifically, Figs. 3A and 6A illustrate that the second lower gate structure LE2 and the first upper gate structure UE1, which are disposed adjacent the interface between the lower transistor CH1 and the upper transistor CH2, each have a thickness t2. Ha further teaches that the first lower gate structure LE1 has a thickness t1 greater than t2, and illustrates that the uppermost gate structure UE4 is thicker than UE1. Accordingly, Ha teaches that the first gate structure (LE2) and the second gate structure (UE1) have thicknesses that are less than thicknesses of remaining gate structures (e.g., LE1 and UE4) of the plurality of gate structures (Figs. 3A and 6A; [0075]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the gate structures of Park so that the gate structures adjacent the semiconductor layer have reduced thicknesses as taught by Ha, in order to improve electrical characteristics of the semiconductor device, including reducing operating voltage and improving device reliability, as expressly taught by Ha [0075]. Such modification merely applies a known gate thickness configuration to achieve its recognized and predictable advantages.
Furthermore, applicant's specification does not identify any criticality associated with the claimed relative gate thickness relationship, nor does it demonstrate any unexpected result arising from making the first and second gate structures thinner than remaining gate structures. Accordingly, adopting the relative gate thicknesses taught by Ha would have been an obvious design choice yielding predictable results.
Regarding claim 20. Park discloses The semiconductor device of claim 18. But Park does not expressly disclose wherein thicknesses of the two or more gate structures are less than thicknesses of remaining ones of the plurality of gate structures.
However, Ha discloses a semiconductor device including a plurality of gate structures having different thicknesses. Specifically, Figs. 3A and 6A illustrate that the second lower gate structure (LE2) and the first upper gate structure (UE1), which are disposed adjacent the interface between the lower transistor (CH1) and the upper transistor (CH2), each have a thickness t2. Ha further teaches that the first lower gate structure (LE1) has a thickness t1 greater than t2, and further illustrates that the uppermost gate structure (UE4) has a greater thickness than UE1. Accordingly, Ha teaches that the first gate structure (LE2) and the second gate structure (UE1) have thicknesses less than thicknesses of remaining gate structures (e.g., LE1 and UE4) of the plurality of gate structures (Figs. 3A and 6A; [0075]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the gate structures of Park so that the gate structures adjacent the semiconductor layer have reduced thicknesses, as taught by Ha, in order to improve electrical characteristics of the semiconductor device, including reducing operating voltage and improving device reliability, as expressly taught by Ha [0075]. Such modification merely applies a known gate thickness configuration to obtain its recognized and predictable advantages.
Furthermore, applicant's specification does not identify any criticality associated with the claimed relative gate thickness relationship, nor does it demonstrate any unexpected result arising from making the first and second gate structures thinner than the remaining gate structures. Accordingly, adopting the relative gate thicknesses taught by Ha would have been an obvious design choice yielding predictable results.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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