DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the present Application 18/668,486, filed 05/20/2024. Claims 1-20 are pending in the Application, of which Claims 1, 8 and 15 are independent.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/12/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS has been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 2, 3, 5 and 6, the limitations “a voltage difference is sequentially subtracted from a precedent retry read voltage along the second direction”, and “voltage difference is sequentially added on a precedent retry read voltage along the first direction” render the Claims indefinite. The Claims recite the limitations in the passive voice, thus failing to define the device that performs the subtraction of the voltage difference from a previous read voltage. There is no sufficient description in the specification for defining the precedent retry read voltage.
Claims not specifically mentioned above are rejected due to their dependency on a rejected claim.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Independent Claims 1, 8 and 15 recite an abstract idea directed to a group of mathematical concepts, under Step 2A Prong 1, of the 2019 Revised Patent Subject Matter Eligibility Guidance, according to the limitations,
applying a first read voltage to the memory device and calculating a first absolute difference between the number of a first bit value and the number of a second bit value corresponding to the first read voltage;
applying a second read voltage to the memory device and calculating a second absolute difference between the number of the first bit value and the number of the second bit value corresponding to the second read voltage, which a first voltage difference is between the second read voltage and the first read voltage along a first direction; and
comparing the first absolute difference and the second absolute difference;
wherein, upon determining the second absolute difference is smaller than the first absolute difference, obtaining at least one retry read voltages by subsequently adding an amount of the first voltage difference on the second read voltage along the first direction, and applying the at least one retry read voltages to the memory device until a read data obtained by one of the retry read voltages passing an ECC decoding;
wherein, upon determining the second absolute difference is greater than the first absolute difference, obtaining at least one retry read voltages by subsequently subtracting the amount of the first voltage difference from the first read voltage along a second direction which is opposite to the first direction, and applying the at least one retry read voltages to the memory device until a read data obtained by one of the retry read voltages passing the ECC decoding.
The limitations recited in the Claims, which as drafted, are directed to a group of mathematical concepts. According to the 2019 Revised Patent Subject Matter Eligibility Guidance (“2019 PEG”), under their broadest reasonable interpretation, the limitations cover performance of mathematical concepts, such as, mathematical relationships, mathematical formulas or equations, and mathematical calculations.
If a claim limitation, under its broadest reasonable interpretation, covers performance of mathematical calculations, then it falls within the “Mathematical Concepts” of abstract ideas. For example, the above limitations as drafted, is a process that, under its broadest reasonable interpretation, covers performance of mathematical relationships but for the recitation of a “processor”, such as NAND flash controller 131 comprising a CPU, recited in independent Claim 15 and shown in Fig. 1.
For example, the limitations as recited in independent Claim 1, “calculating a first absolute difference between the number of a first bit value and the number of a second bit value” and “calculating a second absolute difference between the number of the first bit value and the number of the second bit value” is directed to a mathematical calculation that falls in the group of mathematical concepts.
The limitations recited in Claim 1, “obtaining at least one retry read voltages by subsequently adding an amount of the first voltage difference on the second read voltage along the first direction” and “obtaining at least one retry read voltages by subsequently subtracting the amount of the first voltage difference from the first read voltage along a second direction which is opposite to the first direction” are mathematical expressions. For example, addition, usually denoted with the plus sign +, and subtraction denoted with the minus sign – are the two of the four basic operations of arithmetic, and therefore are part of a group of mathematical concepts.
This judicial exception is not integrated into a practical application, under Step 2A Prong 2, of the 2019 Revised Patent Subject Matter Eligibility Guidance. In particular, the claim recites additional elements using a “processor” to perform operations. In this case, the processor in all steps is recited at a high-level of generality (i.e., as a generic processor performing a generic computer function) such that it amounts no more than mere software instructions to apply the exception using a generic computer component. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of using a processor to perform instructions amounts to no more than mere software instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The claim is not patent eligible.
Additionally, the software instructions must produce a useful, concrete and tangible result, otherwise the claims fail the 35 U.S.C. 101 statutory requirement. The software constitutes an abstract idea without any tangible results, and without further reciting any practical applications, for achieving such results.
Dependent Claims 2-7, 9-14 and 16-20 recite no additional limitations that would amount to significantly more than the abstract idea defined in its respective independent claims. The dependent Claims recite mathematical concepts similar to those in the independent Claims, i.e. adding and subtracting arithmetic operations.
For example, Claims 2, 3, 5 and 6, the limitations “a voltage difference is sequentially subtracted from a precedent retry read voltage”, and “voltage difference is sequentially added on a precedent retry read voltage” are associated with arithmetic operations, and therefore are part of a group of mathematical concepts.
The claimed invention does not include significantly more than the judicial exception because performing arithmetic operations does not satisfy the requirements of subject matter eligibility under 35 USC 101.
Accordingly, for the reasons provided above, claims 1-20 are directed to an abstract idea, hence, not patent eligible under 35 USC 101.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
(US 9,437,315) Lee; Hyung Min. Referring to FIG. 8 , the control circuit 220 includes a read retry table 222. As described above, the read retry table 222 includes an order of the change of the read voltage when the read operation is repeatedly performed. A voltage difference between the read voltages is uniform. The control circuit 220 changes the read voltage according to the read voltage order in the read retry table 222 to perform the read operation. When the read operation is passed, the control circuit 220 stores the read voltage and the direction during the performance of the read operation.
(US 20220326884) KANG; Woohyun et al. [0214] When it is determined in operation S343 that the raw data have an uncorrectable error (“Yes”), the storage controller may again perform operation S342. For example, the storage controller may perform a first read retry operation based on a first read retry voltage; when raw data of the first read retry operation have an uncorrectable error, the storage controller may determine a second read retry voltage based on a page count value of the raw data of the first read retry operation, and may perform a second read retry operation based on the second read retry voltage.
(US 11869614) Goode; Jonas et al. FIG. 3 is a diagram 300 illustrating a CSG 302 of FIG. 1. The CSG 302 receives a left sense 304a and a right sense 304b for a wordline of an NVM, such as the NVM 110 of FIG. 1. The left sense 304a may be the left sense 254, and the right sense 304b may be the right sense 264 of FIG. 2B. Because the left sense 304a and the right sense 304b are iterative senses, the plurality of left senses are accumulated at a first adder 306a for cells of a wordline of the NVM 110, and the plurality of right senses are accumulated at a second adder 306b for the same cells of the wordline of the NVM 110.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: April 14, 2026
Non-Final Rejection 20260408
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
Prosecution Insights