DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Information disclosure statement filed 5/20/2024 and 1/26/2025 have been considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5, 7-8, 10, 14, 16-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent Application No. US 2023/0408767 A1 to Kita et al. (hereinafter “Kita”).
Regarding claim 1, Kita discloses a chip package, comprising: a package substrate (e.g. 206A in Fig. 2B) having a first side and a second side, wherein the package substrate comprises a dielectric substrate or a silicon interposer (paragraph [0038]); an optical engine (209+203 in Fig. 2B) bonded to the first side, wherein the optical engine comprises an electrical integrated circuit die (209 in Fig. 2B) and a photonic integrated circuit die (203 in Fig. 2B) in a vertical stack, and the photonic integrated circuit die comprises an edge coupler (204 in Fig. 2B; paragraph [0033]); and a fiber mounting unit (217 in Fig. 2B) bonded to the first side adjacent the optical engine, wherein the fiber mounting unit holds an optical fiber (201 in Fig. 2B) in alignment with the edge coupler.
Regarding claim 2, Kita discloses a heat spreader (i.e. thermally conductive material 218 in Fig. 2D; paragraph [0041]) over the photonic integrated circuit die (203 in Fig. 2D).
Regarding claim 3, Kita discloses an embodiment where the electrical integrated circuit die (901 in Fig. 9) is over the photonic integrated circuit die (203 in Fig. 9).
Regarding claim 5, Kita discloses wherein the photonic integrated circuit die defines a cavity (i.e. 202 of 204 in Fig. 2E), and a core of the optical fiber extends from the fiber mounting unit into the cavity (i.e. 201 extends into 204 as shown in Fig. 2B).
Regarding claim 7, Kita discloses wherein the optical fiber is embedded in the fiber mounting unit (paragraph [0032]).
Regarding claim 8, Kita discloses wherein the optical fiber is within a fiber array unit (215 in Fig. 7) held by the fiber mounting unit (Fig. 2B).
Regarding claim 10, Kita discloses wherein the fiber mounting unit is glued to the first side (see 216 in Fig. 2B).
Regarding claim 14, Kita discloses wherein the package substrate is a silicon interposer (paragraph [0039]).
Regarding claim 16, Kita discloses a chip package, comprising: a package substrate (e.g. 206 in Fig. 2B), wherein the package substrate comprises a dielectric substrate or a silicon interposer (paragraph [0038]); an optical engine (209+203 in Fig. 2B) comprising a photonic integrated circuit die (203 in Fig. 2B) and an electrical integrated circuit die (209 in Fig. 2B) mounted to and electrically coupled with the package substrate (i.e. coupled via solder- paragraph [0038]), wherein the photonic integrated circuit die comprises an edge coupler (204 in Fig. 2B; paragraph [0033]); and a fiber mounting unit (217 in Fig. 2B), wherein the fiber mounting unit is mounted to the package substrate side-by-side with the optical engine (Fig. 2B) and has a first cavity (necessarily present as the optical fiber is disposed in 217 as disclosed) positioned to hold an optical fiber in alignment with the edge coupler.
Regarding claim 17, Kita discloses wherein the photonic integrated circuit die comprises a second cavity (202 in 204 as shown in Fig. 2E) positioned to hold an optical fiber in alignment with the edge coupler.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4, 6, 9, 11, 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kita.
Regarding claim 4, Kita discloses a chip package according to claim 1 as already discussed above. In addition to the above, Kita discloses the photonic integrated circuit die disposed over the electrical integrated circuit die (Fig. 2B). However, it does not explicitly disclose the use of a second electrical integrated circuit die bonded to and over the electrical integrated circuit die, in the manner claimed in the present application. On the other hand, the use of a second electrical integrated circuit die is well known and common in the art. Such use of a second integrated circuit die would be readily recognized as advantageous and desirable to one of ordinary skill in the art because it would allow for modular addition of signal processing circuits (such as transimpedance amplifiers, etc.) to be added without the need for replacing or redesigning the existing integrated circuit. Therefore, it would have been obvious to a person of ordinary skill in the art before the filing date of the present application to modify the device of Kita to have a second electrical integrated circuit die bonded to and over the electrical integrated circuit die, in the manner claimed in the present application.
Regarding claim 6, Kita discloses a chip package according to claim 1 as already discussed above. However, Kita does not explicitly disclose the cladding of the optical fiber being stripped from the core at an end of the optical fiber that is within the fiber mounting unit as claimed in the present application. On the other hand, use of a stripped optical fiber core is well known and common in the art. The use of a stripped bare optical fiber would allow for accurate mode field coupling between the optical fiber end and a planar waveguide core and allow for a high coupling precision. Therefore, it would have been obvious to a person of ordinary skill in the art before the filing date of the present application to modify the device of Kita to have the cladding of the optical fiber being stripped from the core at an end of the optical fiber that is within the fiber mounting unit as claimed in the present application.
Regarding claims 9 and 11, Kita discloses a chip package according to claim 1 as already discussed above. However, Kita does not explicitly disclose the fiber mounting unit being soldered or bonded by dielectric-to-dielectric bonding to the first side as claimed in the present application. On the other hand, both the use of a solder and the use of a dielectric-to-dielectric bonding are well known and common in the art. Solder bonding is well known to be advantageous because it provides a strong and rigid mechanical coupling, and dielectric-to-dielectric bonding allows for formation of seamless stacked structures for high density optical package. Therefore, it would have been obvious to a person of ordinary skill in the art before the filing date of the present application to modify the device of Kita to have the fiber mounting unit being soldered or bonded by dielectric-to-dielectric bonding to the first side as claimed in the present application.
Regarding claim 18, Kita discloses a chip package according to claim 1 as already discussed above. As such Kita necessarily discloses a method of making such a chip package, including the steps of forming an optical engine (209+203 in Fig. 2B) that comprises an electrical integrated circuit die (209 in Fig. 2B) bonded to a photonic integrated circuit die (203 in Fig. 2B) in a vertical stack; mounting the optical engine on a package substrate (e.g. 206 in Fig. 2B), wherein the package substrate comprises a dielectric substrate or a silicon interposer paragraph [0038]); mounting a fiber mounting unit (217 in Fig. 2B) on the package substrate; and mounting the end portion in alignment with an edge coupler (204 in Fig. 2B) of the photonic integrated circuit die, wherein the fiber mounting unit holds the end portion (Fig. 2B).
However, it does not explicitly disclose a step of stripping cladding from an end portion of an optical fiber to provide an exposed core, in the manner claimed in the present application. On the other hand, using a stripped optical fiber core (thereby a step of stripping a cladding from the optical fiber core) is well known and common in the art. The use of a stripped bare optical fiber would allow for accurate mode field coupling between the optical fiber end and a planar waveguide core and allow for a high coupling precision. Therefore, it would have been obvious to a person of ordinary skill in the art before the filing date of the present application to modify the device of Kita to have the cladding of the optical fiber being stripped from the core at an end of the optical fiber that is within the fiber mounting unit as claimed in the present application.
Regarding claim 19, Kita renders the method of assembling a chip packaged claimed in claim 18 obvious as already discussed above. In addition, Kita discloses the end portion of the optical fiber being inserted into a cavity formed in the photonic integrated circuit die (i.e. 202 of 204 in Fig. 2E). As such, Kita also renders obvious the claimed subject matter of claim 19.
Claim(s) 12-13, 15, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kita in view of US Patent No. 10,365,447 B2 to Mekis et al. (hereinafter “Mekis”).
Regarding claims 12-13, Kita discloses a chip package according to claim 1 as already discussed above. However, it does not explicitly disclose the fiber mounting unit being the same height as the optical engine, or a chip stack bonded to the first side, wherein the chip stack and the optical engine being coextensive in height, as claimed in the present application.
On the other hand, such features are known in the art, and disclosed by Mekis. Mekis discloses an optical package wherein a fiber mounting unit (115 in Fig. 1) is the same height as the optical engine (114 in Fig. 1), and it also discloses a chip stack (120,124 in Fig. 1; column 4, lines 48-55) bonded to the first side of the package substrate, wherein the chip stack and the optical engine are coextensive in height (Fig. 1). One of ordinary skill in the art would readily recognize such coextensive height features as advantageous and desirable since it would allow for simplified flip-chip and die bonding process due to the planar surface of the optical package, as well as reduced tolerance stacking since vertical tolerance errors wouldn’t compound across multiple components due to the coextensive height. Therefore, it would have been obvious to a person of ordinary skill in the art before the filing date of the present application to modify the device of Kita to have the fiber mounting unit being the same height as the optical engine, or a chip stack bonded to the first side, wherein the chip stack and the optical engine being coextensive in height, as claimed in the present application.
Regarding claim 15, Kita discloses a chip package according to claim 1 as already discussed above. However, it does not explicitly disclose the use of a printed circuit board, and a fixture attached to the circuit board supporting the optical fiber, in the manner claimed in the present application.
On the other hand, the use of a printed circuit board with a chip package is known in the art. Also, various fixtures for supporting optical fibers are known in the art. For example, Mekis discloses an optical package wherein an electro optic chip package is mounted on a printed circuit board (172 in Fig. 3). The use of a printed circuit board is well known to be advantageous since it allows for enhanced integration of multiple optoelectronic components. Additionally, although Mekis does not explicitly disclose that a fiber support fixture is attached to the printed circuit board, such a fixture is well known. One of ordinary skill in the art would readily recognize the advantage of using such a fixture since it would allow for secure and stable optical fiber coupling with minimal coupling loss. Therefore, it would have been obvious to a person of ordinary skill in the art before the filing date of the present application to modify the device of Kita to have a printed circuit board, and a fixture attached to the circuit board supporting the optical fiber, in the manner claimed in the present application.
Regarding claim 20, Kita renders the method of assembling a chip packaged claimed in claim 18 obvious as already discussed above. However, it does not explicitly disclose the mounting of the package substrate to a printed circuit board, and attaching a fixture to the printed circuit board for supporting the optical fiber as claimed in the present application. On the other hand, the use of a printed circuit board with a chip package is known in the art. Also, various fixtures for supporting optical fibers are known in the art. For example, Mekis discloses an optical package wherein an electro optic chip package is mounted on a printed circuit board (172 in Fig. 3). The use of a printed circuit board is well known to be advantageous since it allows for enhanced integration of multiple optoelectronic components. Additionally, although Mekis does not explicitly disclose that a fiber support fixture is attached to the printed circuit board, such a fixture is well known. One of ordinary skill in the art would readily recognize the advantage of using such a fixture since it would allow for secure and stable optical fiber coupling with minimal coupling loss. Therefore, it would have been obvious to a person of ordinary skill in the art before the filing date of the present application to modify the device of Kita to have a printed circuit board, and a fixture attached to the circuit board supporting the optical fiber, in the manner claimed in the present application.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG H PAK whose telephone number is (571)272-2353. The examiner can normally be reached M-F: 7AM- 5PM.
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/SUNG H PAK/Primary Examiner, Art Unit 2874
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